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ORCIDSpencer K. Millican
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2020 – today
- 2024
[j4]Soham Roy
, Spencer K. Millican, Vishwani D. Agrawal:
A Survey and Recent Advances: Machine Intelligence in Electronic Testing. J. Electron. Test. 40(2): 139-158 (2024)- 2022
- [j3]Yang Sun, Spencer K. Millican:
Applying Artificial Neural Networks to Logic Built-in Self-test: Improving Test Point Insertion. J. Electron. Test. 38(4): 339-352 (2022) - 2021
- [c20]Spencer K. Millican, SueAnne Griffith:
A study of transistor degradation in cyber-physical system control devices: work-in-progress. CODES+ISSS 2021: 37-38 - [c19]Soham Roy, Spencer K. Millican, Vishwani D. Agrawal:
Unsupervised Learning in Test Generation for Digital Integrated Circuits. ETS 2021: 1-4 - [c18]Ayokunle Fadamiro, Pouyan Rezaie, Spencer K. Millican, Christopher Harris:
Simulating and Evaluating a Quaternary Logic FPGA Based on Floating-gate Memories and Voltage Division. FPGA 2021: 226 - [c17]Ayokunle Fadamiro, Pouyan Rezaie, Spencer K. Millican, Christoper B. Harris:
A Pragmatic Quaternary FPGA Implemented with Floating Gate Memories. ISMVL 2021: 166-171 - [c16]Soham Roy, Spencer K. Millican, Vishwani D. Agrawal:
Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator. VLSID 2021: 316-321 - [c15]Soham Roy, Spencer K. Millican, Vishwani D. Agrawal:
Special Session - Machine Learning in Test: A Survey of Analog, Digital, Memory, and RF Integrated Circuits. VTS 2021: 1-14 - 2020
- [j2]Soham Roy, Brandon Stiene, Spencer K. Millican, Vishwani D. Agrawal:
Improved Pseudo-Random Fault Coverage Through Inversions: a Study on Test Point Architectures. J. Electron. Test. 36(1): 123-133 (2020) - [c14]Ayokunle Fadamiro, Pouyan Rezaie, Christopher Harris, Spencer K. Millican:
A Quaternary FPGA Architecture Using Floating Gate Memories. FCCM 2020: 227 - [c13]Soham Roy, Spencer K. Millican, Vishwani D. Agrawal:
Machine Intelligence for Efficient Test Pattern Generation. ITC 2020: 1-5 - [c12]Joshua Immanuel, Spencer K. Millican:
Calculating Signal Controllability using Neural Networks: Improvements to Testability Analysis and Test Point Insertion. NATW 2020: 1-6 - [c11]Yang Sun, Spencer K. Millican, Vishwani D. Agrawal:
Special Session: Survey of Test Point Insertion for Logic Built-in Self-test. VTS 2020: 1-6
2010 – 2019
- 2019
- [c10]Spencer K. Millican, Yang Sun, Soham Roy, Vishwani D. Agrawal:
Applying Neural Networks to Delay Fault Testing: Test Point Insertion and Random Circuit Training. ATS 2019: 13-18 - [c9]Yang Sun, Spencer K. Millican:
Test Point Insertion Using Artificial Neural Networks. ISVLSI 2019: 253-258 - [c8]Sankaran M. Menon, Ashish Gupta, Chinna Prudvi, Rolf Kühnis, Sukhbinder Singh Takhar, Spencer K. Millican, Eric Rentschler, Pandy Kalimuthu, Preeti Ranjan Panda, Priyadarsan Patra:
Techniques for Debug of Low Power SoCs. MTV 2019: 45-49 - [c7]Soham Roy, Brandon Stiene, Spencer K. Millican, Vishwani D. Agrawal:
Improved Random Pattern Delay Fault Coverage Using Inversion Test Points. NATW 2019: 1-6 - [c6]Jubayer Mahmod, Spencer K. Millican, Ujjwal Guin, Vishwani D. Agrawal:
Special Session: Delay Fault Testing - Present and Future. VTS 2019: 1-10 - 2015
- [c5]Spencer K. Millican, Kewal K. Saluja:
Optimal Test Scheduling of Stacked Circuits under Various Hardware and Power Constraints. VLSID 2015: 487-492 - 2014
- [j1]Spencer K. Millican, Kewal K. Saluja:
Optimal Test Scheduling Formulation under Power Constraints with Dynamic Voltage and Frequency Scaling. J. Electron. Test. 30(5): 569-580 (2014) - [c4]Spencer K. Millican, Kewal K. Saluja:
A Test Partitioning Technique for Scheduling Tests for Thermally Constrained 3D Integrated Circuits. VLSID 2014: 20-25 - [c3]Spencer K. Millican, Parameswaran Ramanathan, Kewal K. Saluja:
CryptIP: An Approach for Encrypting Intellectual Property Cores with Simulation Capabilities. VLSID 2014: 92-97 - 2013
- [c2]Spencer K. Millican, Kewal K. Saluja:
Formulating Optimal Test Scheduling Problem with Dynamic Voltage and Frequency Scaling. Asian Test Symposium 2013: 165-170 - 2012
- [c1]Spencer K. Millican, Kewal K. Saluja:
Linear Programming Formulations for Thermal-Aware Test Scheduling of 3D-Stacked Integrated Circuits. Asian Test Symposium 2012: 37-42
Coauthor Index
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last updated on 2024-07-05 20:09 CEST by the dblp team
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