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ORCIDShane T. Fleming
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2020 – today
- 2024
[j3]Junyi Liu
, Aleksandar Dragojevic, Shane T. Fleming, Antonios Katsarakis, Dario Korolija, Igor Zablotchi, Ho-Cheung Ng, Anuj Kalia, Miguel Castro:
Honeycomb: Ordered Key-Value Store Acceleration on an FPGA-Based SmartNIC. IEEE Trans. Computers 73(3): 857-871 (2024)- 2023
- [j2]Andrew D. Brown, Jonathan R. Beaumont, David B. Thomas, Julian C. Shillcock, Matthew Naylor, Graeme M. Bragg, Mark Vousden, Simon W. Moore, Shane T. Fleming:
POETS: An Event-driven Approach to Dissipative Particle Dynamics: Implementing a Massively Compute-intensive Problem on a Novel Hard/Software Architecture. ACM Trans. Parallel Comput. 10(2): 7:1-7:32 (2023) - 2022
- [j1]Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason Helge Anderson, John Wickerson, George A. Constantinides:
Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code. IEEE Trans. Computers 71(4): 933-946 (2022) - 2021
- [c16]Matthew Naylor, Simon W. Moore, David B. Thomas, Jonathan R. Beaumont, Shane T. Fleming, Mark Vousden, A. Theodore Markettos, Thomas Bytheway, Andrew D. Brown:
General hardware multicasting for fine-grained message-passing architectures. PDP 2021: 126-133 - 2020
- [c15]Matthew Naylor, Simon W. Moore, Andrey Mokhov, David B. Thomas, Jonathan R. Beaumont, Shane T. Fleming, A. Theodore Markettos, Thomas Bytheway, Andrew D. Brown:
Termination detection for fine-grained message-passing architectures. ASAP 2020: 17-24
2010 – 2019
- 2019
- [c14]Jianyi Cheng, Shane T. Fleming, Yu Ting Chen, Jason Helge Anderson, George A. Constantinides:
EASY: Efficient Arbiter SYnthesis from Multi-threaded Code. FPGA 2019: 142-151 - [c13]Qiang Li, Erwei Wang, Shane T. Fleming, David B. Thomas, Peter Y. K. Cheung:
Accelerating Position-Aware Top-k ListNet for Ranking Under Custom Precision Regimes. FPL 2019: 81-87 - 2018
- [c12]Shane T. Fleming, David B. Thomas:
Injecting FPGA Configuration Faults in Parallel. FPT 2018: 198-205 - [c11]Qiang Li, Shane T. Fleming, David B. Thomas, Peter Y. K. Cheung:
Accelerating Top-k ListNet Training for Ranking Using FPGA. FPT 2018: 242-245 - 2017
- [c10]Shane T. Fleming, David B. Thomas:
Using Runahead Execution to Hide Memory Latency in High Level Synthesis. FCCM 2017: 109-116 - [c9]Nadesh Ramanathan, Shane T. Fleming, John Wickerson, George A. Constantinides:
Hardware Synthesis of Weakly Consistent C Concurrency. FPGA 2017: 169-178 - 2016
- [c8]Shane T. Fleming, David B. Thomas:
StitchUp: automatic control flow protection for high level synthesis circuits. DAC 2016: 138:1-138:6 - 2015
- [c7]David B. Thomas, Shane T. Fleming, George A. Constantinides, Dan R. Ghica:
Transparent linking of compiled software and synthesized hardware. DATE 2015: 1084-1089 - [c6]Shane T. Fleming, David B. Thomas, George A. Constantinides, Dan R. Ghica:
System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System. FPGA 2015: 214-217 - [c5]Shane T. Fleming, Ivan Beretta, David B. Thomas, George A. Constantinides, Dan R. Ghica:
PushPush: Seamless integration of hardware and software objects via function calls over AXI. FPL 2015: 1-8 - 2014
- [c4]Shane T. Fleming, David B. Thomas:
Heterogeneous Heartbeats: A framework for dynamic management of Autonomous SoCs. FPL 2014: 1-6 - [c3]Gordon Inggs, Shane T. Fleming, David B. Thomas, Wayne Luk:
Is high level synthesis ready for business? A computational finance case study. FPT 2014: 12-19 - 2013
- [c2]Shane T. Fleming, David B. Thomas:
Hardware Acceleration of Matrix Multiplication over Small Prime Finite Fields. ARC 2013: 103-114 - [c1]Shane T. Fleming, David B. Thomas:
FPGA based control for real time systems. FPL 2013: 1-2
Coauthor Index
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