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ORCIDFPT 2014: Shanghai, China
- Jialin Chen, Wenbo Yin, Yuichiro Shibata, Lingli Wang, Hayden Kwok-Hay So, Yuchun Ma:
2014 International Conference on Field-Programmable Technology, FPT 2014, Shanghai, China, December 10-12, 2014. IEEE 2014, ISBN 978-1-4799-6245-7
Keynote Lectures
- Mike Butts:
Logic emulation in the megaLUT era - Moore's Law beats Rent's Rule. 1 - Jason Cong:
Automating customized computing. 2 - Feng-Hsiung Hsu:
Doing FPGA in a former software company. 3
1.1 Tools & Design Productivity
- Marcel Gort, Jason Helge Anderson:
Design re-use for compile time reduction in FPGA high-level synthesis flows. 4-11 - Gordon Inggs
, Shane T. Fleming, David B. Thomas, Wayne Luk:
Is high level synthesis ready for business? A computational finance case study. 12-19 - Rafat Rashid, J. Gregory Steffan, Vaughn Betz:
Comparing performance, productivity and scalability of the TILT overlay processor to OpenCL HLS. 20-27 - Junying Huang, Colin Yu Lin, Yang Liu, Zhihua Li, Haigang Yang:
Size aware placement for island style FPGAs. 28-35 - Chang Xu, Wentai Zhang, Guojie Luo:
Analyzing the impact of heterogeneous blocks on FPGA placement quality. 36-43
1.2 Financial Applications
- Aryan Tavakkoli, David B. Thomas:
Low-latency option pricing using systolic binomial trees. 44-51 - Jinzhe Yang, Ce Guo, Wayne Luk, Terence Nahar:
Collaborative processing of Least-Square Monte Carlo for American options. 52-59 - Shengjia Shao, Ce Guo, Wayne Luk, Stephen Weston:
Accelerating transfer entropy computation. 60-67 - Mark de Jong, Vlad Mihai Sima, Koen Bertels, David Thomas:
FPGA-accelerated Monte-Carlo integration using stratified sampling and Brownian bridges. 68-75
1.3 Architecture & Runtime Systems
- Benjamin Carrión Schäfer:
Time sharing of Runtime Coarse-Grain Reconfigurable Architectures processing elements in multi-process systems. 76-82 - Shaoyi Cheng, John Wawrzynek:
Architectural synthesis of computational pipelines with decoupled memory access. 83-90 - Hongyuan Ding, Miaoqing Huang:
Improve memory access for achieving both performance and energy efficiencies on heterogeneous systems. 91-98 - Charles Eric LaForest, Jason Helge Anderson, J. Gregory Steffan:
Approaching overhead-free execution on FPGA soft-processors. 99-106
2.1 Mathematical Circuits
- Björn Liebig, Andreas Koch:
Low-latency double-precision floating-point division for FPGAs. 107-114 - Kan Shi, David Boland, George A. Constantinides:
Efficient FPGA implementation of digit parallel online arithmetic operators. 115-122 - Jianfeng Zhang, Paul Chow, Hengzhu Liu:
An efficient FPGA implementation of QR decomposition using a novel systolic array architecture based on enhanced vectoring CORDIC. 123-130 - Andreas Ehliar:
Area efficient floating-point adder and multiplier with IEEE-754 compatible semantics. 131-138 - Wenqiang Wang, Kaiyuan Guo, Mengyuan Gu, Yuchun Ma, Yu Wang:
A universal FPGA-based floating-point matrix processor for mobile systems. 139-146
2.2 Special Session: Hardware Security
- Jiliang Zhang, Gang Qu:
A survey on security and trust of FPGA-based systems. 147-152 - He Li, Qiang Liu:
Hardware Trojan detection acceleration based on word-level statistical properties management. 153-160 - Jianlei Yang, Chenguang Wang, Yici Cai, Qiang Zhou:
Power supply noise aware evaluation framework for side channel attacks and countermeasures. 161-166 - Tobias Wiersema, Stephanie Drzevitzky, Marco Platzner:
Memory security in reconfigurable computers: Combining formal verification with monitoring. 167-174 - Duncan J. M. Moss, Zhe Zhang, Nicholas J. Fraser, Philip Heng Wai Leong:
An FPGA-based spectral anomaly detection system. 175-182
3.1 Applications & Devices
- Albert Kwon, Kaiyu Zhang, Perk Lun Lim, Yuchen Pan, Jonathan M. Smith, André DeHon:
RotoRouter: Router support for endpoint-authorized decentralized traffic filtering to prevent DoS attacks. 183-190 - Shuanglong Liu, Grigorios Mingas, Christos-Savvas Bouganis:
Parallel resampling for particle filters on FPGAs. 191-198 - Otávio Alcântara de Lima Júnior, Virginie Fresse, Frédéric Rousseau:
Evaluation of SNMP-like protocol to manage a NoC emulation platform. 199-206 - Xifan Tang, Pierre-Emmanuel Gaillardon, Giovanni De Micheli:
A high-performance low-power near-Vt RRAM-based FPGA. 207-214 - Kosuke Tatsumura, Masato Oda, Shinichi Yasuda:
A pure-CMOS nonvolatile multi-context configuration memory for dynamically reconfigurable FPGAs. 215-222
Poster Session I: Application
- Oliver Sander, Steffen Baehr, Enno Lübbers, Timo Sandmann, Viet Vu Duy, Jürgen Becker:
A flexible interface architecture for reconfigurable coprocessors in embedded multicore systems using PCIe Single-root I/O virtualization. 223-226 - Theepan Moorthy, Sathish Gopalakrishnan:
Gigabyte-scale alignment acceleration of biological sequences via Ethernet streaming. 227-230 - Yun Wu, José L. Núñez-Yáñez, Roger F. Woods, Dimitrios S. Nikolopoulos:
Power modelling and capping for heterogeneous ARM/FPGA SoCs. 231-234 - Hui Yan Cheah, Suhaib A. Fahmy, Nachiket Kapre:
Analysis and optimization of a deeply pipelined FPGA soft processor. 235-238 - Mrinal J. Sarmah, Syed Azeemuddin:
A circuit to synchronize high speed serial communication channel. 239-242 - Server Kasap, Soydan Redif:
Novel reconfigurable hardware implementation of polynomial matrix/vector multiplications. 243-247 - Xian Yang, Ray C. C. Cheung:
A complementary architecture for high-speed true random number generator. 248-251 - Siddhartha, Nachiket Kapre:
Fanout decomposition dataflow optimizations for FPGA-based Sparse LU factorization. 252-255 - Shanker Shreejith, Suhaib A. Fahmy:
Zero latency encryption with FPGAs for secure time-triggered automotive networks. 256-259 - Zhilei Chai, Haojie Zhou, Zhibin Wang, Dong Wu:
Using C to implement high-efficient computation of dense optical flow on FPGA-accelerated heterogeneous platforms. 260-263 - Gopinath Mahale, Hamsika Mahale, Rajesh Babu Parimi, S. K. Nandy, S. Bhattacharya:
Hardware architecture of bi-cubic convolution interpolation for real-time image scaling. 264-267 - Yi Wang, Akash Kumar, Yajun Ha:
FPGA-based high throughput XTS-AES encryption/decryption for storage area network. 268-271 - Susumu Mashimo, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Zyndroid: An Android platform for software/hardware coprocessing. 272-275 - Andrei Bara, Xinyu Niu, Wayne Luk:
A dataflow system for anomaly detection and analysis. 276-279
Poster Session II: PhD Forum
- Jian Yan, Junqi Yuan, Ying Wang, Philip H. W. Leong, Lingli Wang:
Design space exploration for FPGA-based hybrid multicore architecture. 280-281 - Brahim Al Farisi, Karel Heyse, Dirk Stroobandt:
Reducing the overhead of dynamic partial reconfiguration for multi-mode circuits. 282-283 - Yidi Liu, Benjamin Carrión Schäfer:
HW acceleration of multiple applications on a single FPGA. 284-285 - Fubing Mao, Wei Zhang, Bingsheng He:
Towards automatic partial reconfiguration in FPGAs. 286-287 - Eric Shun Fukuda, Hiroaki Inoue, Takashi Takenaka, Dahoo Kim, Tsunaki Sadahisa, Tetsuya Asai, Masato Motomura:
Achieving higher performance of memcached by caching at network interface. 288-289 - Jiasen Huang, Junyan Ren, Wenbo Yin, Lingli Wang:
No zero padded sparse matrix-vector multiplication on FPGAs. 290-291
Poster Session III: Architecture & Tools
- Tassadaq Hussain, Oscar Palomar, Osman S. Unsal, Adrián Cristal, Eduard Ayguadé, Mateo Valero, Shakaib A. Gursal:
AMMC: Advanced Multi-Core Memory Controller. 292-295 - Fredrik Brosser, Emil Milh, Vilhelm Geijer, Per Larsson-Edefors:
Assessing scrubbing techniques for Xilinx SRAM-based FPGAs in space applications. 296-299 - Niranjan Kulkarni, Jinghua Yang, Sarma B. K. Vrudhula:
A fast, energy efficient, field programmable threshold-logic array. 300-305 - Takuya Kajiwara, Qian Zhao, Motoki Amagasaki, Masahiro Iida, Morituro Kuga, Toshinori Sueyoshi:
A novel three-dimensional FPGA architecture with high-speed serial communication links. 306-309 - Young-Hwan Park, Keshava Prasad, Yeonbok Lee, Kitaek Bae, Ho Yang:
Scalable radio processor architecture for modern wireless communications. 310-313 - David de la Chevallerie, Jens Korinth, Andreas Koch:
Integrating FPGA-based processing elements into a runtime for parallel heterogeneous computing. 314-317 - Ameer M. S. Abdelhadi, Guy G. F. Lemieux:
Deep and narrow binary content-addressable memories using FPGA-based BRAMs. 318-321 - Anthony Milton, David A. Kearney, Sebastien C. Wong, Simon Lemmo:
Development productivity in implementing a complex heterogeneous computing application. 322-325 - Quentin Gautier, Alexandria Shearer, Janarbek Matai, Dustin Richmond, Pingfan Meng, Ryan Kastner:
Real-time 3D reconstruction for FPGAs: A case study for evaluating the performance, area, and programmability trade-offs of the Altera OpenCL SDK. 326-329 - Guohao Dai, Yi Shan, Fei Chen, Yu Wang, Kun Wang, Huazhong Yang:
Online scheduling for FPGA computation in the Cloud. 330-333 - Yongfu He, Shaojun Wang, Yu Peng, Yeyong Pang, Ning Ma, Jingyue Pang:
High performance relevance vector machine on HMPSoC. 334-337 - Bin Tang, Yaping Lin, Jiliang Zhang:
Improving the reliability of RO PUF using frequency offset. 338-341
Demo Session
- Siyi Qiao, Chen Xu, Lei Xie, Ji Yang, Chengchen Hu, Xiaohong Guan, Jianhua Zou:
Network recorder and player: FPGA-based network traffic capture and replay. 342-345 - Ning Ma, Shaojun Wang, Yeyong Pang, Yu Peng:
Implementation of LS-SVM with HLS on Zynq. 346-349 - Jiahua Chen, Tao Wang, Haoyang Wu, Jian Gong, Xiaoguang Li, Yang Hu, Gaohan Zhang, Zhiwei Li, Junrui Yang, Songwu Lu:
A high-performance and high-programmability reconfigurable wireless development platform. 350-353 - Yu Fujita, Koichiro Masuyama, Hideharu Amano:
Image processing by A 0.3V 2MW coarse-grained reconfigurable accelerator CMA-SOTB with a solar battery. 354-357
Design Competition
- Naru Sugimoto, Hideharu Amano:
Hardware/software co-design architecture for Blokus Duo solver. 358-361 - Hossein Borhanifar, Seyed Peyman Zolnouri:
Optimize MinMax algorithm to solve Blokus Duo game by HDL. 362-365 - Javier Olivito, Alberto Delmas, Javier Resano:
An improved FPGA-based specific processor for Blokus Duo. 366-369 - Ehsan Qasemi, Amir Samadi, Mohammad H. Shadmehr, Bardia Azizian, Sajjad Mozaffari, Amir Shirian, Bijan Alizadeh:
Highly scalable, shared-memory, Monte-Carlo tree search based Blokus Duo Solver on FPGA. 370-373 - Susumu Mashimo, Kansuke Fukuda, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Blokus Duo engine on a Zynq. 374-377 - Akira Kojima:
FPGA implementation of Blokus Duo player using hardware/software co-design. 378-381
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