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2020 – today
- 2022
[j8]Saeid Daneshgar
, Hao Li, Taehwan Kim, Ganesh Balamurugan:
A 128 Gb/s, 11.2 mW Single-Ended PAM4 Linear TIA With 2.7 μArms Input Noise in 22 nm FinFET CMOS. IEEE J. Solid State Circuits 57(5): 1397-1408 (2022)
2010 – 2019
- 2018
- [j7]Kaushik Dasgupta, Saeid Daneshgar, Chintan Thakkar, Shinwon Kang, Anandaroop Chakrabarti, Shuhei Yamada, Nathan Narevsky, Debabani Choudhury, James E. Jaussi, Bryan Casper:
A 60-GHz Transceiver and Baseband With Polarization MIMO in 28-nm CMOS. IEEE J. Solid State Circuits 53(12): 3613-3627 (2018) - [c7]Shinwon Kang, Chintan Thakkar, Nathan Narevsky, Kaushik Dasgupta, Saeid Daneshgar, James E. Jaussi, Bryan Casper:
A 40Gb/s 6pJ/b RX baseband in 28nm CMOS for 60GHz polarization MIMO. ISSCC 2018: 164-166 - [c6]Saeid Daneshgar, Kaushik Dasgupta, Chintan Thakkar, Anandaroop Chakrabarti, Shuhei Yamada, Debabani Choudhury, James E. Jaussi, Bryan Casper:
A 27.8Gb/s 11.5pJ/b 60GHz transceiver in 28nm CMOS with polarization MIMO. ISSCC 2018: 166-168 - 2017
- [c5]Kaushik Dasgupta, Saeid Daneshgar, Chintan Thakkar, Kunal Datta, James E. Jaussi, Bryan Casper:
A 25 Gb/s 60 GHz digital power amplifier in 28nm CMOS. ESSCIRC 2017: 207-210 - 2015
- [j6]Kristian N. Madsen, Timothy D. Gathman, Saeid Daneshgar, Thomas C. Oh, James Chingwei Li, James F. Buckwalter:
A High-Linearity, 30 GS/s Track-and-Hold Amplifier and Time Interleaved Sample-and-Hold in an InP-on-CMOS Process. IEEE J. Solid State Circuits 50(11): 2692-2702 (2015) - 2014
- [j5]Hyun-Chul Park, Saeid Daneshgar, Zach Griffith, Miguel Urteaga, Byung-Sung Kim, Mark J. W. Rodwell:
Millimeter-Wave Series Power Combining Using Sub-Quarter-Wavelength Baluns. IEEE J. Solid State Circuits 49(10): 2089-2102 (2014) - [j4]Saeid Daneshgar, Zach Griffith, Munkyo Seo, Mark J. W. Rodwell:
Low Distortion 50 GSamples/s Track-Hold and Sample-Hold Amplifiers. IEEE J. Solid State Circuits 49(10): 2114-2126 (2014) - 2011
- [j3]Saeid Daneshgar, Oscar De Feo, Michael Peter Kennedy:
Observations Concerning the Locking Range in a Complementary Differential LC Injection-Locked Frequency Divider - Part II: Design Methodology. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(4): 765-776 (2011) - 2010
- [j2]Saeid Daneshgar, Oscar De Feo, Michael Peter Kennedy:
Observations Concerning the Locking Range in a Complementary Differential LC Injection-Locked Frequency Divider - Part I: Qualitative Analysis. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(1): 179-188 (2010) - [j1]Paolo Maffezzoni, Dario D'Amore, Saeid Daneshgar, Michael Peter Kennedy:
Analysis and Design of Injection-Locked Frequency Dividers by Means of a Phase-Domain Macromodel. IEEE Trans. Circuits Syst. I Regul. Pap. 57-I(11): 2956-2966 (2010) - [c4]Saeid Daneshgar, Michael Peter Kennedy:
A qualitative analysis of a complementary differential LC injection-locked frequency divider based on direct injection. ISCAS 2010: 1531-1534 - [c3]Paolo Maffezzoni, Dario D'Amore, Saeid Daneshgar, Michael Peter Kennedy:
Estimating the locking range of analog dividers through a phase-domain macromodel. ISCAS 2010: 1535-1538
2000 – 2009
- 2008
- [c2]Saeid Daneshgar, Michael Peter Kennedy:
Design methodology for a divide-by-4 LC injection-locked frequency divider based on nonlinear analysis. ICECS 2008: 1139-1142 - 2007
- [c1]Mohammad M. Ghahramani, Saeid Daneshgar, Michael Peter Kennedy, Oscar De Feo:
Optimizing the design of an injection-locked frequency divider by means of nonlinear analysis. ECCTD 2007: 571-574
Coauthor Index
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