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ORCIDErfan Azarkhish
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2020 – today
- 2022
[j6]Petar Jokic
, Erfan Azarkhish, Andrea Bonetti, Marc Pons, Stéphane Emery, Luca Benini:
A Construction Kit for Efficient Low Power Neural Network Accelerator Designs. ACM Trans. Embed. Comput. Syst. 21(5): 56:1-56:36 (2022)- 2021
- [c7]Komail M. H. Badami, Marc Pons Solé, Erfan Azarkhish, André Fivaz, Michaël Rapin, Olivier Chételat, Stéphane Emery:
Single-Battery Cooperative Sensors For Multi-Lead Long Term Ambulatory ECG Measurement. BioCAS 2021: 1-4 - [c6]Petar Jokic, Erfan Azarkhish, Régis Cattenoz, Engin Türetken, Luca Benini, Stéphane Emery:
A Sub-mW Dual-Engine ML Inference System-on-Chip for Complete End-to-End Face-Analysis at the Edge. VLSI Circuits 2021: 1-2 - [i2]Petar Jokic, Erfan Azarkhish, Andrea Bonetti, Marc Pons, Stéphane Emery, Luca Benini:
A Construction Kit for Efficient Low Power Neural Network Accelerator Designs. CoRR abs/2106.12810 (2021)
2010 – 2019
- 2019
- [c5]Marc Pons Solé, Andre Bischof, Lorenzo Bergamini, Philippe Dallemagne, Stéphane Emery, Komail M. H. Badami, Jiang Deng, Themistoklis Mavrogordatos, Erfan Azarkhish, Loïc Zahnd, Costantino Cosentino, Marcin K. Augustyniak, Yingyun Zha:
A 20 Channel EMG SoC with an Integrated 32b RISC Core for Real-Time Wireless Prosthetic Control. ESSCIRC 2019: 73-76 - 2018
- [j5]Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini:
Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes. IEEE Trans. Parallel Distributed Syst. 29(2): 420-434 (2018) - 2017
- [j4]Maryam Payami, Erfan Azarkhish, Igor Loi, Luca Benini:
A Hybrid Instruction Prefetching Mechanism for Ultra Low-Power Multicore Clusters. IEEE Embed. Syst. Lett. 9(4): 125-128 (2017) - [j3]Erfan Azarkhish, Christoph Pfister, Davide Rossi, Igor Loi, Luca Benini:
Logic-Base Interconnect Design for Near Memory Computing in the Smart Memory Cube. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 210-223 (2017) - [i1]Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini:
Neurostream: Scalable and Energy Efficient Deep Learning with Smart Memory Cubes. CoRR abs/1701.06420 (2017) - 2016
- [b1]Erfan Azarkhish:
Memory Hierarchy Design for Next Generation Scalable Many-core Platforms. University of Bologna, Italy, 2016 - [c4]Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini:
Design and Evaluation of a Processing-in-Memory Architecture for the Smart Memory Cube. ARCS 2016: 19-31 - 2015
- [j2]Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini:
A Modular Shared L2 Memory Design for 3-D Integration. IEEE Trans. Very Large Scale Integr. Syst. 23(8): 1485-1498 (2015) - [c3]Erfan Azarkhish, Davide Rossi, Igor Loi, Luca Benini:
High performance AXI-4.0 based interconnect for extensible smart memory cubes. DATE 2015: 1317-1322 - 2013
- [j1]Erfan Azarkhish, Igor Loi, Luca Benini:
A case for three-dimensional stacking of tightly coupled data memories over multi-core clusters using low-latency interconnects. IET Comput. Digit. Tech. 7(5): 191-199 (2013) - [c2]Erfan Azarkhish, Igor Loi, Luca Benini:
A high-performance multiported L2 memory IP for scalable three-dimensional integration. 3DIC 2013: 1-8 - [c1]Erfan Azarkhish, Igor Loi, Luca Benini:
3D logarithmic interconnect: Stacking multiple L1 memory dies over multi-core clusters. NOCS 2013: 1-2
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