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Yoshichika Fujioka
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2010 – 2019
- 2014
- [c5]Shintaro Harada, Xu Bai, Michitaka Kameyama, Yoshichika Fujioka:
Design of a Logic-in-Memory Multiple-Valued Reconfigurable VLSI Based on a Bit-Serial Packet Data Transfer Scheme. ISMVL 2014: 214-219 - 2012
- [c4]Yoshichika Fujioka, Michitaka Kameyama:
Configuration memory size reduction of a Dynamically Reconfigurable Processor based on a register-transfer-level packet data transfer scheme. ISOCC 2012: 235-238
2000 – 2009
- 2009
- [c3]Nobuhiro Tomabechi, Yoshichika Fujioka:
Traveling-salesman game with multiple competitors/cooperators and simultaneous move search algorithm. ICE-GIC 2009: 223-230 - 2005
- [c2]Yuya Homma, Michitaka Kameyama, Yoshichika Fujioka, Nobuhiro Tomabechi:
VLSI architecture based on packet data transfer scheme and its application. ISCAS (2) 2005: 1786-1789 - 2000
- [j5]Yoshichika Fujioka, Nobuhiro Tomabechi:
Design of a WSI scale parallel processor for intelligent robot control based on a dynamic reconfiguration of multi-operand arithmetic units. Syst. Comput. Jpn. 31(12): 33-42 (2000)
1990 – 1999
- 1999
- [j4]Yoshichika Fujioka, Michitaka Kameyama:
Design of a reconfigurable VLSI processor for robot control based on bit-serial architecture. Syst. Comput. Jpn. 30(12): 43-51 (1999) - 1996
- [j3]Michitaka Kameyama, Yoshichika Fujioka:
VLSI Processor System for Robotics. J. Robotics Mechatronics 8(6): 496-499 (1996) - [j2]Yoshichika Fujioka, Nobuhiro Tomabechi:
Design of a Parallel Processor for Visual Feedback Control Based on the Reconfiguration of Word Length. J. Robotics Mechatronics 8(6): 524-530 (1996) - 1994
- [j1]Yoshichika Fujioka, Michitaka Kameyama, Tatsuo Higuchi:
Coordinate Transformation VLSI Processor for Redundant Manipulator Control. J. Robotics Mechatronics 6(2): 124-130 (1994) - 1993
- [c1]Yoshichika Fujioka, Michitaka Kameyama:
2400-MFLOPS Reconfigurable Parallel VLSI Processor for Robot Control. ICRA (3) 1993: 149-154
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