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Jai Gopal Pandey
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2020 – today
- 2024
- [j6]Kartik Jhawar, Jugal Gandhi
, Diksha Shekhawat
, Aniket Upadhyay, Avadh Harkishanka, Nitin Chaturvedi, M. Santosh, Jai Gopal Pandey:
Modeling, hardware architecture, and performance analyses of an AEAD-based lightweight cipher. J. Real Time Image Process. 21(2): 32 (2024) - [c22]Kuntal Chakraborty, Jai Gopal Pandey, Abir J. Mondal:
Design and Analysis of an Area and Power Efficient Programmable Delay Cell. VLSID 2024: 31-36 - [c21]Jugal Gandhi
, Rishi Agarwal, Anish Mall, Diksha Shekhawat
, M. Santosh, Jai Gopal Pandey:
SAT and SCOPE Attacks on Deceptive Multiplexer Logic Locking. VLSID 2024: 547-552 - 2023
- [j5]Jugal Gandhi
, Diksha Shekhawat
, M. Santosh, Jai Gopal Pandey:
Logic locking for IP security: A comprehensive analysis on challenges, techniques, and trends. Comput. Secur. 129: 103196 (2023) - [c20]Jugal Gandhi
, Diksha Shekhawat
, M. Santosh, Jai Gopal Pandey:
LOKI: A Secure FPGA Prototyping of IoT IP with Lightweight Logic Locking. APCCAS 2023: 85-89 - [c19]Diksha Shekhawat
, Jugal Gandhi
, M. Santosh
, Jai Gopal Pandey
:
PHAc: Posit Hardware Accelerator for Efficient Arithmetic Logic Operations. CoNGA 2023: 88-100 - [c18]Jugal Gandhi
, Diksha Shekhawat
, M. Santosh, Jai Gopal Pandey:
Security Evaluation of Lightweight SBoxes. iSES 2023: 315-318 - [i1]Ruby Kumari, Jai Gopal Pandey, Abhijit Karmakar:
An RTL Implementation of the Data Encryption Standard (DES). CoRR abs/2301.05530 (2023) - 2022
- [c17]Rudresh Pratap Singh
, Shreyam Kumar, Jai Gopal Pandey
:
An Overlap-and-Add Based Time Domain Acceleration of CNNs on FPGA-CPU Systems. VDAT 2022: 573-583 - 2021
- [j4]Jai Gopal Pandey
:
An embedded FPGA-SoC framework and its usage in moving object tracking application. Des. Autom. Embed. Syst. 25(3): 213-236 (2021) - [j3]Apoorva Jangir
, Jai Gopal Pandey
:
GIFT cipher usage in image data security: hardware implementations, performance and statistical analyses. J. Real Time Image Process. 18(6): 2551-2567 (2021) - [c16]Diksha Shekhawat
, Apoorva Jangir, Jai Gopal Pandey:
A Hardware Generator for Posit Arithmetic and its FPGA Prototyping. VDAT 2021: 1-6 - 2020
- [c15]Jai Gopal Pandey, Sanskriti Gupta, Abhijit Karmakar
:
A Unified Architecture for AES/PRESENT Ciphers and its Usage in an SoC Environment. LASCAS 2020: 1-4 - [c14]Jai Gopal Pandey, Ayush Laddha, Sashwat Deb Samaddar:
A Lightweight VLSI Architecture for RECTANGLE Cipher and its Implementation on an FPGA. VDAT 2020: 1-6 - [c13]Sahan Panguluru, Jai Gopal Pandey:
A Highly Stable and Robust 7T SRAM Cell using Memristor. VDAT 2020: 1-4
2010 – 2019
- 2019
- [j2]Jai Gopal Pandey
, Tarun Goel, Abhijit Karmakar
:
Hardware architectures for PRESENT block cipher and their FPGA implementations. IET Circuits Devices Syst. 13(7): 958-969 (2019) - [j1]Sajid Khan
, Ambika Prasad Shah
, Neha Gupta, Shailesh Singh Chouhan, Jai Gopal Pandey, Santosh Kumar Vishvakarma
:
An ultra-low power, reconfigurable, aging resilient RO PUF for IoT applications. Microelectron. J. 92 (2019) - [c12]Jai Gopal Pandey, Chhavi Mitharwal, Abhijit Karmakar
:
An RNS Implementation of the Elliptic Curve Cryptography for IoT Security. TPS-ISA 2019: 66-72 - [c11]Sajid Khan
, Neha Gupta, Abhinav Vishwakarma, Shailesh Singh Chouhan, Jai Gopal Pandey, Santosh Kumar Vishvakarma:
Dual-Edge Triggered Lightweight Implementation of AES for IoT Security. VDAT 2019: 298-307 - [c10]Sajid Khan
, Neha Gupta, Gopal Raut
, Gunjan Rajput, Jai Gopal Pandey, Santosh Kumar Vishvakarma:
An Ultra Low Power AES Architecture for IoT. VDAT 2019: 334-344 - [c9]Victor Jeffry Louis, Jai Gopal Pandey
:
A Novel Design of SRAM Using Memristors at 45 nm Technology. VDAT 2019: 579-589 - 2018
- [c8]Jai Gopal Pandey, Tarun Goel, Mausam Nayak, Chhavi Mitharwal, Abhijit Karmakar
, Raj Singh:
A High-Performance VLSI Architecture of the Present Cipher and its Implementations for SoCs. SoCC 2018: 96-101 - [c7]Jai Gopal Pandey, Tarun Goel, Mausam Nayak, Chhavi Mitharwal, Sajid Khan
, Santosh Kumar Vishvakarma
, Abhijit Karmakar
, Raj Singh:
A VLSI Architecture for the PRESENT Block Cipher with FPGA and ASIC Implementations. VDAT 2018: 210-220 - [c6]Jai Gopal Pandey, Tarun Goel, Abhijit Karmakar
:
A High-Performance and Area-Efficient VLSI Architecture for the PRESENT Lightweight Cipher. VLSID 2018: 392-397 - 2017
- [c5]Jai Gopal Pandey, Tarun Goel, Abhijit Karmakar
:
An Efficient VLSI Architecture for PRESENT Block Cipher and Its FPGA Implementation. VDAT 2017: 270-278 - 2015
- [c4]Jai Gopal Pandey, Arindam Karmakar, Chandra Shekhar, S. Gurunarayanan:
An embedded framework for accurate object localization using center of gravity measure with mean shift procedure. VDAT 2015: 1-6 - [c3]Jai Gopal Pandey, Arindam Karmakar, Chandra Shekhar, S. Gurunarayanan:
An FPGA-Based Architecture for Local Similarity Measure for Image/Video Processing Applications. VLSID 2015: 339-344 - 2014
- [c2]Jai Gopal Pandey, Arindam Karmakar, S. Gurunarayanan:
Architectures and algorithms for image and video processing using FPGA-based platform. VDAT 2014: 1 - [c1]Jai Gopal Pandey, Arindam Karmakar, Chandra Shekhar, S. Gurunarayanan:
A Novel Architecture for FPGA Implementation of Otsu's Global Automatic Image Thresholding Algorithm. VLSID 2014: 300-305
Coauthor Index
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last updated on 2024-08-05 20:25 CEST by the dblp team
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