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ORCID37th VLSI Design 2024: Kolkata, India
- 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, VLSID 2024, Kolkata, India, January 6-10, 2024. IEEE 2024, ISBN 979-8-3503-8440-6
- Shriharsh Prasad Behera, Mahesh Vaidya, Alok Naugarhiya:
Low Loss Gate Engineered Superjunction Insulated Gate Bipolar Transistor for High Speed Application. 1-5 - Alba Ordonez Rodriguez, Fabien Gilibert, Francois Paolini, Pascal Urard, Roberto Guizzetti, John Samuel
, Remy Cellier, Lioua Labrak, Bastien Deveautour:
Artificial neural network-based solution for PSP MOSFET model card extraction. 6-12 - Monika Kumari, Manodipan Sahoo:
Sensitivity Enhancement of TMD MOSFET-Based Biosensor by Modeling and Optimization of Back Gate Parameters. 13-18 - Om Maheshwari, Dev Vyas, Nihar Ranjan Mohapatra:
K-means Clustering with ANN based Classification to Predict Current-Voltage Characteristics of Advanced FETs. 19-24 - Shivendra Singh, Ekta Tiwari, Abhinav Gupta, Sneh Saurabh:
Improving Retention Time of 1T DRAM using Electrostatic Barrier: Proposal and Analysis. 25-30 - Kuntal Chakraborty, Jai Gopal Pandey, Abir J. Mondal:
Design and Analysis of an Area and Power Efficient Programmable Delay Cell. 31-36 - Indranil Maity, Shivam Das, Malay Gangopadhyay, Indrajit Maity:
Understanding 2-Propanol Sensing Mechanism of Pd Modified Graphene Based Gas Sensor Devices using DFT Study. 37-42 - S. Sarath, Darshni Manekar, Rajendra P. Shukla, Chandan Yadav:
Design of MoS2 based Inverter Circuits considering Interface Trap effect. 43-48 - Vivek Kumar, Nischal Anand, Rohit Rai, Sneha Chauhan, Jyoti Patel:
Unveiling Thermal Cross Talk in 5nm Gate-All-Around Stacked Nanosheet FETs: A Machine Learning Perspective. 49-54 - Pranav Jain, Gagandeep, Sneh Saurabh:
FLIP: An Artificial Neural Network-based Post-routing Incremental Placer. 55-60 - J. Dhurga Devi, Bama Srinivasan, Selvi Ravindran, Ranjani Parthasarathi, P. V. Ramakrishna, Lakshmanan Balasubramanian:
Machine Learning based Waveform Predictions using Discrete Wavelet Transform for Automated Verification of Analog and Mixed Signal Integrated Circuits. 61-66 - Amartya Dutta, Riya Majumder, Rajat Kumar Pal:
Reinforcement Learning based Droplet Routing Technique in Hexagonal Digital Microfluidic Biochips using Dueling Network. 67-72 - Jahnvi Singh, Nijwm Wary, Pradip Mandal:
Use of current-mode and voltage-mode receivers together for on-chip multipoint-to-multipoint data transmission across global interconnects. 73-78 - Srujana Krishnamurthy Pillay:
A 0.8V, Tri-State Inverter based SRAM Cell for SoC Applications. 79-83 - Sandipan Sinha, Manish Trivedi, Jaswinder Singh, Sriharsha Enjapuri, Deepesh Gujjar, Ramesh Halli, Girishankar Gurumurthy:
A 3nm Ultra High-Speed (4.5GHz) SRAM Cache Design With Wide DVFS Range. 84-89 - Marichamy Divya, Siva Kumar Rapina, S. Kumaravel:
Phase frequency detector with zero-reset pulse for low-spur Phase-locked loop applications. 90-95 - Sumit Kumar, Gaurab Banerjee:
An Improved Charge-Pump Design to Increase Tuning Range and Reduce Spurs in FMCW Radar Synthesizers. 96-100 - Chilaka Jayaram, Sreehari Rao Patri:
A sub-μW Fully Integrated Compact CMOS Temperature Sensor for Passive RFID Applications. 101-106 - Nidhee Bhuwal, Kamal Solanki, Manoj Kumar Majumder, Deepika Gupta:
Flux Controlled Grounded Meminductor Emulator Using Single DVCCTA. 107-112 - Tamal Chowdhury, Pradip Mandal:
A Neuro Inspired Pulse Density Modulator Sensing Unipolar and Bipolar Current Signals. 113-118 - Ishan Mishra, Ganpat Anant Parulekar, Shalabh Gupta:
A Compact Low-Power 29 Gb/s Pseudo Random Quaternary Sequence Generator in 65 nm CMOS. 119-124 - Albert Daimari, Ankit Chakusaru Deori, Amab Ratna Pawe, Ratul Kumar Baruah:
Design of 3 bit/cell NAND Memory Array Based on Ferroelectric Field Effect Transistor. 125-128 - Sowmyashree S, Hitesh Shrimali:
An On-chip Thermoelectric Cooler Controller With Improved Driving Current of 2 A at 0.5 Ω Load. 129-134 - Minal Bisen, Kapil Jainwal, Nitin Khanna:
Design and Implementation of SPAD-Based Linearly Stable Multi-Mode Configurable TAC Pixel. 135-139 - Indrajit Das, Hari Kishore Kakara, Vasudeva Reddy, Venkata Vanukuru:
A 7.1 GHz +23.7 dBm OIP3 1-dB NF Cascode LNA for next-generation Wi-Fi using a 130 nm SOI CMOS Technology. 140-144 - Gopikrishna Vijayakumar, Alok Joshi, Abhishek Kumar:
A 1.6 - 2.5 GHz Receiver for Software Defined Radio with High Linearity Mode. 145-149 - Zainubia, Bipul Kumar Singh, Manish Pundir, Subhash Chander Dubey, Ambika Prasad Shah:
Parallel-Series Diode-based Ring Amplifier for Switched Capacitor Circuits. 150-155 - Anshul Verma, Bishnu Prasad Das:
A Low Power Dual-Band Sub-Sampling Phase Locked Loop with sub-100 fs RMS Jitter and jitter. 156-161 - Jyoti Priya, Darshak Bhatt:
A Low Power and Low Noise, Self Body Biased Low Noise Amplifier. 162-167 - Sanchari Das, Bibhu Datta Sahoo:
Closed Form Expression of Input Matching of a Wideband Single-Ended to Differential LNA. 168-173 - Sayan Sarkar, Abhishek Anand:
An Integrated Multipurpose Low-Power Electrochemical Readout Interface with On-Chip Input Waveform Generator. 174-179 - Davide Giacomini, Maeesha Binte Hashem, Jeremiah Suarez, Amit Ranjan Trivedi:
Towards Model-Size Agnostic, Compute-Free, Memorization-based Inference of Deep Learning. 180-185 - Amisha Srivastava, Sneha Thakur, Abraham Peedikayil Kuruvila, Poras T. Balsara, Kanad Basu:
Hardware-based Detection of Malicious Firmware Modification in Microgrids. 186-191 - Abhishek Ramdas Nair, Pallab Kumar Nath, Shantanu Chakrabartty, Chetan Singh Thakur:
Multiplierless In-filter Computing for tinyML Platforms. 192-197 - Subhadeep Dolai, Ekata Mitra:
Optimizing Medical Image Analysis: Leveraging Efficient Hardware and AI Algorithms. 198-203 - Manu Rathore, Garrett S. Rose:
SpiCS-Net: Circuit Switched Network on Chip for Area-Efficient Spiking Recurrent Neural Networks. 204-209 - Md. Najrul Islam, Rahul Shrestha, Shubhajit Roy Chowdhury:
Low-Complexity lassification Technique and Hardware-Efficient Classify-Unit Architecture for CNN Accelerator. 210-215 - Zeeshan Anwar, Imlijungla Longchar, Hemangee K. Kapoor:
Bit-Beading: Stringing bit-level MAC results for Accelerating Neural Networks. 216-221 - Sathwika Bavikadi, Purab Ranjan Sutradhar, Amlan Ganguly, Sai Manoj Pudukotai Dinakarrao:
Reconfigurable Processing-in-Memory Architecture for Data Intensive Applications. 222-227 - Soumendu Kumar Ghosh, Shamik Kundu, Arnab Raha, Deepak A. Mathaikutty, Vijay Raghunathan:
HARVEST: Towards Efficient Sparse DNN Accelerators using Programmable Thresholds. 228-234 - Syed Asrar ul Haq, Varun Singh, Bhanu Teja Tanaji, Sumit Darak:
Low Complexity High Speed Deep Neural Network Augmented Wireless Channel Estimation. 235-240 - Saketh Gajawada, Aryan Gupta, Kailash Prasad, Joycee Mekie:
FP-BMAC: Efficient Approximate Floating-Point Bit-Parallel MAC Processor using IMC. 241-246 - Yathin Kumar Attuluri, Ruchit Chudasama, Kailash Prasad, Joycee Mekie:
FP-ATM: A Flexible Floating Point NOR Adder Tree Macro for In-Memory Computing. 247-252 - Vrajesh Patel, Neel Shah, Aravind Krishna, Tom Glint, Abdul Ronak, Joycee Mekie:
COMPRIZE: Assessing the Fusion of Quantization and Compression on DNN Hardware Accelerators. 253-258 - Shengjie Xu, Clara Hobbs, Bineet Ghosh, Parasara Sridhar Duggirala, Samarjit Chakraborty:
Certifiable and Efficient Autonomous Cyber-Physical Systems Design. 259-263 - Kaustabha Ray, Ansuman Banerjee:
Autonomous Automotives on the Edge. 264-269 - Suraj Singh, Somnath Hazra, Sumanta Dey, Soumyajit Dey:
Certifying Learning-Enabled Autonomous Cyber Physical Systems - A Deployment Perspective. 270-275 - Anand Yeolekar, Ravindra Metta, Samarjit Chakraborty:
SMT-based Control Safety Property Checking in Cyber-Physical Systems under Timing Uncertainties. 276-280 - Sashank Nishad, Santanu Kundu, Nicolas Richaud, S. Mallikarjun, Manoranjan Prasad, Lennart Renker:
MLESD: Machine Learning Assisted Faster On-Chip ESD Convergence Strategy. 281-286 - Manoranjan Prasad, Santanu Kundu, Lennart Renker, Rakesh Ranjan:
Unlocking the Power of Machine Learning for Faster PCB Package and Board PDN Convergence. 287-292 - Vinod Viswanath, Kanad Chakraborty:
DFT Static Verification using Early RTL Exploration and Debug for Mobile SoC and Edge AI Applications. 293-299 - Pooja Beniwal, Sneh Saurabh:
Artificial Neural Network-based Prediction and Alleviation of Congestion during Placement. 300-305 - Sneha Lahiri, Megha Kesh, Rupsa Mandal, Anirban Bhattacharjee, Sovan Bhattacharya, Dola Sinha, Chandan Bandyopadhyay, Laxmidhar Biswal, Robert Wille, Rolf Drechsler:
A Dynamic Programming Based Graph Traversal Approach for Efficient Implementation of Nearest Neighbor Architecture in 2D. 306-311 - Saloni Tandon:
A method to accurately simulate and detect transition time instants in piecewise linear SMPS circuits. 312-317 - Swathi Kumar Vembu, Anupam Chattopadhyay, Sayandeep Saha:
Authenticating Edge Neural Network through Hardware Security Modules and Quantum-Safe Key Management. 318-323 - Danny Pereria, Sumana Ghosh, Soumyajit Dey:
DRL-based Multi-Stream Scheduling of Inference Pipelines on Edge Devices. 324-329 - Vijay Kumar, Goldy, Kolin Paul, Mahesh Chowdhary:
Long Short Term Memory (LSTM)-based Cuffless Continuous Blood Pressure Monitoring. 330-335 - Dibya Chowdhury, Shivdeep, Devarshi Mrinal Das:
A Pulse Oximeter and a Controller Designed for Automatic Regulation of Oxygen Concentrators. 336-341 - Sree Ranjani Rajendran, Farimah Farahmandi, Mark Tehranipoor:
CAD Tools Pathway in Hardware Security. 342-347 - Prakhar Diwan, Suryakant Toraskar, Varun Venkitaraman, Nirmal Kumar Boran, Chandramani Chaudhary, Virendra Singh:
MIST: Many-ISA Scheduling Technique for Heterogeneous-ISA Architectures. 348-353 - Debabrata Senapati, Dharmendra Maurya, Arnab Sarkar, Chandan Karfa:
ERS: Energy-efficient Real-time DAG Scheduling on Uniform Multiprocessor Embedded Systems. 354-359 - Debanjan Mallik, Sumana Ghosh:
An Efficient Neural Network Controller for Autonomous Lane-Keeping Assist System. 360-365 - Raj Kumar Choudhary, Janeel Patel, Virendra Singh:
Early Execution for Soft Error Detection. 366-371 - Tamonash Bhattacharyya, Prasun Ghosal, Sonam, Sujay Deb:
Vigil: A RISC-V SoC Architecture for 2-fold Hybrid CNN-kNN based Fall Detector Implementation on FPGA. 372-377 - Ankita Nandi, Pratik Kumar, Shantanu Chakrabartty, Chetan Singh Thakur:
Margin Propagation based Analog Soft-Gates for Probabilistic Computing. 378-383 - Fatemeh Shirinzadeh, Arighna Deb, Saeideh Shirinzadeh, Abhoy Kole, Kamalika Datta, Rolf Drechsler:
In-Memory SAT-Solver for Self-Verification of Programmable Memristive Architectures. 384-389 - Shubham Pande, Bhaswar Chakrabarti, Anjan Chakravorty:
Thermal Crosstalk Analysis in ReRAM Passive Crossbar Arrays. 390-395 - Ritajit Majumdar, Dhiraj Madan, Debasmita Bhoumik, Dhinakaran Vinayagamurthy, Shesha Raghunathan, Susmita Sur-Kolay:
Optimized QAOA ansatz circuit design for two-body Hamiltonian problems. 396-401 - Mohit Kumar, Abhik Kumar Khan, Sudip Roy, Krishnendu Chakrabarty, Sukanta Bhattacharjee:
Accelerating Fluid Loading in Sample Preparation with Fully Programmable Valve Arrays. 402-407 - Soumen Bajpayee, Imon Mukherjee:
Analysis of the Effects of Crosstalk Errors on Various Quantum Circuits. 408-413 - Kanupriya Varshney, Mani Shankar Yadav, Devarshi Mrinal Das, Brajesh Rawat:
Finding a Promising Oxide Material for Resistive Random Access Memory with Graphene Electrode. 414-418 - Tamal Mandal, Debraj Kundu, Sudip Roy:
Retention Time Constrained Bioassay Scheduling on Flow-Based Microfluidic Biochips with Latches. 419-424 - Sumit Saha, Prasad B. Kanyaka, Mark Lust, Nima Ghalichechian, V. Ramgopal Rao, Maryam Shojaei Baghini:
Heterogeneous CMOS-MEMS based Boost Converter for 2.4 GHz RF energy Harvester. 425-430 - Monika Pokharia, Kailash Prasad, Ravi S. Hegde, Joycee Mekie:
Hybrid CMOS-Memristor Logic for Boosting the Power-Efficiency in Error Tolerant Applications. 431-436 - Aruna Jayasena, Prabhat Mishra:
Design for Trust Utilizing Rareness Reduction. 437-442 - Debayan Das, Majid Sabbagh, Rana Elnaggar, Guang Chen, Sayak Ray, Jason M. Fung:
Optimal Placement of TDC Sensor for Enhanced Power Side-Channel Assessment on FPGAS. 443-448 - Akash Panzade, Deepak Kumar, Mahendra Rathor, Urbi Chatterjee:
Vig-WaR: Vigilantly Watching Ransomware for Robust Trapping and Containment. 449-454 - Suraj Mandal, Debapriya Basu Roy:
KiD: A Hardware Design Framework Targeting Unified NTT Multiplication for CRYSTALS-Kyber and CRYSTALS-Dilithium on FPGA. 455-460 - Juneet Kumar Meka, Satya AmarKant Marupureddy, Ranga Vemuri:
Pattern Based Synthetic Benchmark Generation for Hardware Security Applications. 461-466 - Ashutosh Ghimire, Mahommed Alkurdi, Fathi Amsaad:
Enhancing Hardware Trojan Security through Reference-Free Clustering using Representatives. 467-473 - Suryansh Upadhyay, Swaroop Ghosh:
Stealthy SWAPs: Adversarial SWAP Injection in Multi-Tenant Quantum Computing. 474-479 - R. Sivaraman, D. Muralidaran, Rajappa Muthaiah, V. S. Shankar Sriram:
Characteristic Exploitation of Programmable Delay Line Influenced Oscillator Circuit as Hardware Security Primitive. 480-485 - Ayyappa Koppuravuri, Haribabu Pasupuleti, Sasirekha Gvk, Jyotsna Bapat:
A High Throughput ASCON Architecture for Secure Edge IoT Devices. 486-491 - Priyanka Panigrahi, Vignesh Ravichandra Rao, Thockchom Birjit Singha, Chandan Karfa:
SRIL: Securing Registers from Information Leakage at Register Transfer Level. 492-498 - Haimanti Chakraborty, Ranga Vemuri:
ROBUST: RTL OBfuscation USing Bi-functional Polymorphic OperaTors. 499-504 - Nikhil Saxena, Ranga Vemuri:
Enhancing Output Corruption Through GSHE Switch Based Logic Encryption. 505-510 - Vishesh Mishra, Sparsh Mittal, Nirbhay Mishra, Rekha Singhal:
Security Implications of Approximation: A Study of Trojan Attacks on Approximate Adders and Multipliers. 511-516 - Praveen Karmakar, Marpina Bharani, Chandan Karfa:
Evaluating the Robustness of Large scale eFPGA-based Hardware Redaction. 517-522 - Suriya Srinivasan, Ranga Vemuri:
Trojan Localization Using Information Flow Tracking Properties in SoC Designs. 523-528 - Sreenitha Kasarapu, Sathwika Bavikadi, Sai Manoj Pudukotai Dinakarrao:
Processing-in-Memory Architecture with Precision-Scaling for Malware Detection. 529-534 - Kailash Prasad, Neel Shah, Jinay Dagli, Joycee Mekie:
SDR-PUF: Sequence-Dependent Reconfigurable SRAM PUF with an Exponential CRP Space. 535-540 - Joseph Sweeney, Deepali Garg, Lawrence T. Pileggi:
Quantifying the Efficacy of Logic Locking Methods. 541-546 - Jugal Gandhi, Rishi Agarwal, Anish Mall, Diksha Shekhawat, M. Santosh, Jai Gopal Pandey:
SAT and SCOPE Attacks on Deceptive Multiplexer Logic Locking. 547-552 - Manjith Baby Sarojam Chellam, Ramasubramanian Natarajan, Nagi Naganathan:
Logic locking emulator on FPGA: A conceptual view. 553-559 - Gokulnath Rajendran, Furqan Zahoor, Sidhaant Sachin Thakker, Simranjeet Singh, Farhad Merchant, Vikas Rana, Anupam Chattopadhyay:
Harnessing Entropy: RRAM Crossbar-based Unified PUF and RNG. 560-564 - Ankit Bende, Simranjeet Singh, Chandan Kumar Jha, Tim Kempen, Felix Cüppers, Christopher Bengel, Andre Zambanini, Dennis Nielinger, Sachin B. Patkar, Rolf Drechsler, Rainer Waser, Farhad Merchant, Vikas Rana:
Experimental Validation of Memristor-Aided Logic Using 1T1R TaOx RRAM Crossbar Array. 565-570 - Suryansh Upadhyay, Rupshali Roy, Swaroop Ghosh:
Designing Hash and Encryption Engines using Quantum Computing. 571-576 - Chandan Kumar Jha, Sallar Ahmadi-Pour, Rolf Drechsler:
Input Distribution Aware Library of Approximate Adders Based on Memristor-Aided Logic. 577-582 - Noa Aflalo, Eilam Yalon, Shahar Kvatinsky:
Bitwise Logic Using Phase Change Memory Devices Based on the Pinatubo Architecture. 583-586 - Pritam Bhattacharjee, Alak Majumder:
Design of VFC with Programmable Frequency Ramp to control on-chip switching current profile. 587-592 - Dantu Nandini Devi, Gandi Ajay Kumar, Bindu G. Gowda, Madhav Rao:
OEDASA: Optimization Enabled Error-Diluted Approximate Systolic Array Design for an Image Processing Application. 593-598 - Chetan Mittal, Arnab Dey, Anubhab Banerjee, Ashfakh Ali, Zia Abbas:
A 0.8-V, 593-pA Trim-free Duty-cycled All CMOS Current Reference for Ultra-Low Power IoT Applications. 599-604 - Vinay Rayapati, Sanampudi Gopala Krishna Reddy, Gandi Ajay Kumar, Gogireddy Ravi Kiran Reddy, Madhav Rao:
EBACA: Efficient Bfloat16-based Activation Function Implementation Using Enhanced CORDIC Architecture. 605-610 - Ayan Palchaudhuri, Anindya Sundar Dhar:
FPGA Specific Speed-Area Optimized Architectures of Arithmetic Cores with Scan Insertion for Carry Chain Based Multi-level Logic Implementation. 617-622 - Ananya Kapoor, Ayush Thapar, Chaitanya Shanker Jha, Chaudhry Indra Kumar:
A High Performance and Low Power Subthreshold Voltage Level Shifter Design. 623-627 - Somen Adhikary, Ritesh Das, Mousumi Basu:
Broadband spectrum generation in Silicon nanocrystal-based dual-slot waveguide. 628-631 - Atrayee Mishra, Binoy Krishna Ghosh, Dipankar Ghosh, Mousumi Basu:
Generation of Asymmetric Triangular Pulse by A Dispersion and Nonlinearity Engineered Silicon Core Optical Fiber. 632-636 - Sushmita Ghosh, Bidyut K. Bhattacharyya:
A Novel Approach to Control a DC-DC Converter Using its Empirical Physical Model. 637-642 - Enrico Fraccaroli, Seongik Jang, Logan Stach, Hoeseok Yang, Sangyoung Park, Samarjit Chakraborty:
Wear Leveling-Aware Active Battery Cell Balancing. 643-648 - Anup J. Deka, Shobhit Tyagi:
A novel controlled shutdown scheme for DCDC converters enabling energy recycling. 649-654 - Rohan Sinha, Devraj M. Rajagopal, Aditya Madhavan:
Voltage Mode Charge Pump Regulator with Improved Compensation and Dynamic Body Biasing Scheme. 655-659 - Ishan Mishra, Jayaprakash Balachandran, Wen-Sin Liew, Elad Alon, Srinivas Venkataraman, Shalabh Gupta:
Power Integrity Analysis for Interoperability of BoW Chiplet Interfaces. 660-665 - B. Naresh Kumar Reddy, Y. Charan Krishna, P. Naga Satya Nitish, Sitadevi Bharatula:
Optimizing Task Scheduling in Multi-thread Real-Time Systems using Augmented Particle Swarm Optimization. 666-671 - S. Deepanjali, Ayesha Shaik, Noor Mahammad Sk, Beautlin S:
Evolvable Hardware for Fault Mitigation in Control Circuits. 672-677 - Raghavendra Kumar Sakali, Sreehari Veeramachaneni, Sk. Noor Mahammad:
Fault-Tolerant Floating-Point Multiplier Design for Mission Critical Systems. 678-683 - Sabyasachee Banerjee, Subhashis Majumder, Bhargab B. Bhattacharya:
On Managing Test-Time, Power, and Layer Assignment in 3D SoCs with Built-In-Self-Repair Modules. 684-689 - Avishek Choudhury, Brototi Mondal, Kolin Paul, Biplab K. Sikdar:
LLC Block Reuse Predictor Design using Deep Learning to Mitigate Soft Error in Multicore. 690-695 - Soham Roy, Vishwani D. Agrawal:
An Amalgamated Testability Measure Derived from Machine Intelligence. 696-701 - N. Vamshi Krishna, Anushka Chaudhary, Soumya J.:
FGG: Feedback Guided Generation to Accelerate Functional Coverage Closure on Network-on-Chip Processors. 702-707 - Prashant Sonone, Pradeep R:
Structural Testing: Vmin Silicon Issues and Solutions. 708-711 - Haripriya R. S, Soumitro Vyapari, Jaynarayan T. Tudu:
Near-Threshold-at-Gate based Test for Stuck-on Fault in Scan-chain Testing. 712-717 - Ashrith S. Harith, Yingdi Liu, Nilanjan Mukherjee, Jeffrey Mayer:
X-Tolerant Logic BIST for Automotive Designs using Observation Scan Technology. 718-723 - Subhadip Kundu, Jais Abraham:
Revisiting Test Compression Configuration in Context of Multi-Core Testing Using Packetized Scan Network. 724-729 - Tanusree Kaibartta, Hitarth Arora, Debesh Kumar Das:
Genetic Algorithm Based Efficient Grouping Technique for Post Bond Test and Crosstalk Faults Among TSVs. 730-735
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