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ORCIDYutaka Masuda
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2020 – today
- 2024
[j11]Takumi Komori, Yutaka Masuda, Tohru Ishihara:
Virtualizing DVFS for Energy Minimization of Embedded Dual-OS Platform. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(1): 3-15 (2024)- [j10]Jiaxuan Lu, Yutaka Masuda, Tohru Ishihara:
Identification of Redundant Flip-Flops Using Fault Injection for Low-Power Approximate Computing Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 107(3): 540-548 (2024) - 2023
- [j9]Yutaka Masuda, Yusei Honda, Tohru Ishihara:
Dynamic Verification Framework of Approximate Computing Circuits using Quality-Aware Coverage-Based Grey-Box Fuzzing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106(3): 514-522 (2023) - [j8]Lingxiao Hou, Yutaka Masuda, Tohru Ishihara:
An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers for Energy-Efficient Computing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 106(3): 532-541 (2023) - [c18]Jiaxuan Lu, Yutaka Masuda, Tohru Ishihara:
An Efficient Fault Injection Algorithm for Identifying Unimportant FFs in Approximate Computing Circuits. DATE 2023: 1-2 - [c17]Yusei Honda, Yutaka Masuda, Tohru Ishihara:
Feedback-Tuned Fuzzing for Accelerating Quality Verification of Approximate Computing Design. IOLTS 2023: 1-3 - [c16]Tai-Feng Chen, Yutaka Masuda, Tohru Ishihara:
A Standard Cell Memory Based on 2T Gain Cell DRAM for Memory-Centric Accelerator Design. SOCC 2023: 1-6 - 2022
- [j7]TaiYu Cheng, Yutaka Masuda, Jun Nagayama, Yoichi Momiyama, Jun Chen, Masanori Hashimoto:
Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(3): 497-508 (2022) - [j6]Yutaka Masuda, Jun Nagayama, TaiYu Cheng, Tohru Ishihara, Yoichi Momiyama, Masanori Hashimoto:
Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(3): 509-517 (2022) - [j5]Takumi Komori, Yutaka Masuda, Jun Shiomi, Tohru Ishihara:
Approximate Minimum Energy Point Tracking and Task Scheduling for Energy-Efficient Real-Time Computing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 105-A(3): 518-529 (2022) - [c15]Lingxiao Hou, Yutaka Masuda, Tohru Ishihara:
An Accuracy Reconfigurable Vector Accelerator Based on Approximate Logarithmic Multipliers. ASP-DAC 2022: 568-573 - [c14]Naoki Hattori, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi:
Power-aware pruning for ultrafast, energy-efficient, and accurate optical neural network design. DAC 2022: 1285-1290 - [c13]Taisei Ichikawa, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi:
Optoelectronic Implementation of Compact and Power-efficient Recurrent Neural Networks. ISVLSI 2022: 390-393 - [c12]Takumi Komori, Yutaka Masuda, Tohru Ishihara:
DVFS Virtualization for Energy Minimization of Mixed-Criticality Dual-OS Platforms. RTCSA 2022: 128-137 - 2021
- [j4]Naoki Hattori, Jun Shiomi, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi:
Neural Network Calculations at the Speed of Light Using Optical Vector-Matrix Multiplication and Optoelectronic Activation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 104-A(11): 1477-1487 (2021) - [c11]Yutaka Masuda, Jun Nagayama, TaiYu Cheng, Tohru Ishihara, Yoichi Momiyama, Masanori Hashimoto:
Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design. DATE 2021: 1260-1265 - [c10]Kazuki Yoshisue, Yutaka Masuda, Tohru Ishihara:
Dynamic Verification of Approximate Computing Circuits using Coverage-based Grey-box Fuzzing. IOLTS 2021: 1-7 - [c9]Takumi Komori, Yutaka Masuda, Jun Shiomi, Tohru Ishihara:
Integration of Minimum Energy Point Tracking and Soft Real-Time Scheduling for Edge Computing. ISQED 2021: 300-306 - 2020
- [c8]Khyati Kiyawat
, Yutaka Masuda, Jun Shiomi, Tohru Ishihara:
Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy. ISVLSI 2020: 415-421
2010 – 2019
- 2019
- [j3]Yutaka Masuda, Masanori Hashimoto:
MTTF-Aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(7): 867-877 (2019) - [c7]Tohru Ishihara, Jun Shiomi, Naoki Hattori, Yutaka Masuda, Akihiko Shinya, Masaya Notomi:
An Optical Neural Network Architecture based on Highly Parallelized WDM-Multiplier-Accumulator. PHOTONICS@SC 2019: 15-21 - 2018
- [j2]Yutaka Masuda, Takao Onoye, Masanori Hashimoto:
Activation-Aware Slack Assignment for Time-to-Failure Extension and Power Saving. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2217-2229 (2018) - [c6]Yutaka Masuda, Masanori Hashimoto:
MTTF-aware design methodology of error prediction based adaptively voltage-scaled circuits. ASP-DAC 2018: 159-165 - [c5]Yutaka Masuda, Jun Nagayama, Hirotaka Takeno, Yoshimasa Ogawa, Yoichi Momiyama, Masanori Hashimoto:
Comparing voltage adaptation performance between replica and in-situ timing monitors. ICCAD 2018: 39 - 2017
- [j1]Yutaka Masuda, Takao Onoye, Masanori Hashimoto:
Performance Evaluation of Software-Based Error Detection Mechanisms for Supply Noise Induced Timing Errors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(7): 1452-1463 (2017) - 2016
- [c4]Yutaka Masuda, Masanori Hashimoto, Takao Onoye:
Critical path isolation for time-to-failure extension and lower voltage operation. ICCAD 2016: 63 - [c3]Yutaka Masuda, Masanori Hashimoto, Takao Onoye:
Hardware-simulation correlation of timing error detection performance of software-based error detection mechanisms. IOLTS 2016: 84-89 - 2015
- [c2]Yutaka Masuda, Masanori Hashimoto, Takao Onoye:
Performance Evaluation of Software-based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply Noise. ICCAD 2015: 315-322 - [c1]Shoichi Iizuka, Yutaka Masuda, Masanori Hashimoto, Takao Onoye:
Stochastic timing error rate estimation under process and temporal variations. ITC 2015: 1-10
Coauthor Index
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