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ORCIDISVLSI 2022: Nicosia, Cyprus
- IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2022, Nicosia, Cyprus, July 4-6, 2022. IEEE 2022, ISBN 978-1-6654-6605-9
- Samiksha Agarwal, Smruti R. Sarangi:
HAJPAQUE: Hardware Accelerator for JSON Parsing, Querying and Schema Validation. 1-7 - Shalini Singh, Pavan Kumar Pothula, Madhav Rao:
Design and Evaluation of On-chip DCT accelerators based on Novel Approximate Reverse Carry Propagate Adders. 8-13 - Alessio Carpegna, Alessandro Savino
, Stefano Di Carlo:
Spiker: an FPGA-optimized Hardware accelerator for Spiking Neural Networks. 14-19 - Li Lu, Junchao Chen, Markus Ulbricht, Milos Krstic:
A Methodology for Identifying Critical Sequential Circuits with Graph Convolutional Networks. 20-25 - Josie E. Rodriguez Condia, Riccardo Faggiano, Matteo Sonza Reorda:
Microarchitectural Reliability Evaluation of a Block Scheduling Controller in GPUs. 26-31 - Adeboye Stephen Oyeniran, Maksim Jenihhin, Jaan Raik, Raimund Ubar:
High-Level Fault Diagnosis in RISC Processors with Implementation-Independent Functional Test. 32-37 - Lucas Klemmer, Daniel Große:
An Exploration Platform for Microcoded RISC-V Cores leveraging the One Instruction Set Computer Principle. 38-43 - Gianna Paulin, Matheus A. Cavalcante, Paul Scheffler, Luca Bertaccini, Yichao Zhang, Frank K. Gürkaynak, Luca Benini:
Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters. 44-49 - Sina Boroumand, Christos-Savvas Bouganis, George A. Constantinides:
MIDAS: Mutual Information Driven Approximate Synthesis. 50-55 - Mohammad Nazmus Sakib, Rahul Sreekumar, Xinyuan Zhu, Tommy Tracy II, Mircea R. Stan:
Processing-in-Memory with Temporal Encoding. 56-61 - Xi Li, Min Pan, Tong Liu, Peter A. Beerel:
Multi-Phase Clocking for Multi-Threaded Gate-Level-Pipelined Superconductive Logic. 62-67 - Shamiul Alam, Md. Mazharul Islam, Akhilesh Jaiswal, Nathaniel C. Cady, Garrett S. Rose, Ahmedullah Aziz:
Variation-aware Design Space Exploration of Mott Memristor-based Neuristors. 68-73 - Kyle Kuan, Tosiron Adegbija:
A Study of STTRAM-based Page Walker Caches for Energy-Efficient Address Translation. 74-79 - Andrey Laputenko, Nina Yevtushenko, Valentina Andreeva, Anzhela Yu. Matrosova:
Deriving FSM-based tests using $a, b-\text{faults}$ for Logic Circuits. 80-85 - Vojtech Mrazek:
Optimization of BDD-based Approximation Error Metrics Calculations. 86-91 - Martha Schnieber, Saman Fröhlich, Rolf Drechsler:
Polynomial Formal Verification of Approximate Functions. 92-97 - Febin Sunny, Mahdi Nikdast, Sudeep Pasricha:
RecLight: A Recurrent Neural Network Accelerator with Integrated Silicon Photonics. 98-103 - Gang Mao, Alex Yakovlev, Fei Xia, Shengqi Yu, Rishad A. Shafik:
Automated Mapping of Asynchronous Circuits on FPGA under Timing Constraints. 104-109 - Siyu Zhang, Wendong Mao, Zhongfeng Wang:
An Efficient Accelerator of Deformable 3D Convolutional Network for Video Super-Resolution. 110-115 - Sanjay Das, Arun Govindankutty, Shan Deng, Kai Ni, Sumitha George:
Adaptable Multi-level Voltage to Binary Converter Using Ferroelectric FETs. 116-121 - Jun Feng, Shixi Chen, Jiaxu Zhang, Yuxiang Fu, Jiang Xu:
Energy-Efficient High-Performance Photonic Backplane Network for Rack-Scale Computing Systems. 122-127 - Sanmitra Banerjee, Mahdi Nikdast, Sudeep Pasricha, Krishnendu Chakrabarty:
Pruning Coherent Integrated Photonic Neural Networks Using the Lottery Ticket Hypothesis. 128-133 - Amit Mazumder Shuvo, Nitin Pundir, Jungmin Park, Farimah Farahmandi, Mark Tehranipoor:
LDTFI: Layout-aware Timing Fault-Injection Attack Assessment Against Differential Fault Analysis. 134-139 - Nikhil Saxena, Ranga Vemuri:
ISPLock: A Hybrid Internal State Locking Method Using Polymorphic Gates. 140-145 - Anjum Riaz, Gaurav Kumar, Jaynarayan T. Tudu, Satyadev Ahlawat:
On Protecting IJTAG from Data Sniffing and Alteration Attacks. 146-151 - Harideep Nair, Prabhu Vellaisamy, Santha Bhasuthkar, John Paul Shen:
TNN7: A Custom Macro Suite for Implementing Highly Optimized Designs of Neuromorphic TNNs. 152-157 - Nagadastagiri Challapalle, Vijaykrishnan Narayanan:
Performance Evaluation of Video Analytics Workloads on Emerging Processing-In-Memory Architectures. 158-163 - Xiao Li, Lin Chen, Shixi Chen, Fan Jiang, Chengeng Li, Jiang Xu:
Power Management for Chiplet-Based Multicore Systems Using Deep Reinforcement Learning. 164-169 - Dimitris Mouris, Charles Gouert, Nektarios Georgios Tsoutsos:
zk -Sherlock: Exposing Hardware Trojans in Zero-Knowledge. 170-175 - Manju Rajan, Abhijit Das, John Jose:
LOKI: A Hardware Trojan Affecting Multiple Components of an SoC. 176-181 - Minhui Zou, Junlong Zhou, Xiaotong Cui, Wei Wang, Shahar Kvatinsky:
Enhancing Security of Memristor Computing System Through Secure Weight Mapping. 182-187 - Jitka Kocnová, Zdenek Vasícek:
Delay-aware evolutionary optimization of digital circuits. 188-193 - Priyanka Singla, Smruti R. Sarangi:
CmpctArch: A Generic Low Power Architecture for Compact Data Structures in Energy Harvesting Devices. 194-199 - Dionysios Filippas, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
LeapConv: An Energy-Efficient Streaming Convolution Engine with Reconfigurable Stride. 200-205 - Kumari Suravi, Rahul Shrestha:
High-Throughput VLSI Architecture for LDPC Decoder Based on Low-Latency Decoding Technique for Wireless Communication Systems. 206-211 - Lei Yang, Jing Tian, Bo Wu, Zhongfeng Wang, Hao Ren:
An RS-BCH Concatenated FEC Code for Beyond 400 Gb/s Networking. 212-216 - Mattis Hasler, Sebastian Haas, Robert Wittig, Stefan Scholze, Andreas Dixius, Sebastian Höppner, Gerhard P. Fettweis, Christian Mayr:
A Random Linear Network Coding Platform MPSoC Designed in 22nm FDSOI. 217-222 - Khoa Ho, Hui Zhao, Adwait Jog, Saraju P. Mohanty:
Improving GPU Throughput through Parallel Execution Using Tensor Cores and CUDA Cores. 223-228 - Manasa Leela Gummadavelly, Haymanot Gebre-Amlak, Henry Zhu, Sejun Song, Baek-Young Choi:
CosMos: Building A Network Reliability Cost Modeling System for Customer SLA. 229-234 - Wu Yang, Amit Degada, Himanshu Thapliyal:
Adiabatic Logic-based STT-MRAM Design for IoT. 235-240 - Joydeep Dey, Sudeep Pasricha:
Robust Perception Architecture Design for Automotive Cyber-Physical Systems. 241-246 - Deepak Puthal, Ernesto Damiani, Saraju P. Mohanty:
Secure and Scalable Collaborative Edge Computing using Decision Tree. 247-252 - Zhuren Liu, Trevor Exley, Austin Meek, Rachel Yang, Hui Zhao, Mark V. Albert:
Predicting GPU Performance and System Parameter Configuration Using Machine Learning. 253-258 - Saugata Ghose:
The Road to Widely Deploying Processing-in-Memory: Challenges and Opportunities. 259-260 - Geraldo F. Oliveira, Juan Gómez-Luna, Saugata Ghose, Onur Mutlu:
Methodologies, Workloads, and Tools for Processing-in-Memory: Enabling the Adoption of Data-Centric Architectures. 261-266 - Ataberk Olgun, Juan Gómez-Luna, Konstantinos Kanellopoulos, Behzad Salami, Hasan Hassan, Oguz Ergin, Onur Mutlu:
PiDRAM: An FPGA-based Framework for End-to-end Evaluation of Processing-in-DRAM Techniques. 267-272 - Geraldo F. Oliveira, Amirali Boroumand, Saugata Ghose, Juan Gómez-Luna, Onur Mutlu:
Heterogeneous Data-Centric Architectures for Modern Data-Intensive Applications: Case Studies in Machine Learning and Databases. 273-278 - Ivan Fernandez, Ricardo Quislant, Christina Giannoula, Mohammed Alser, Juan Gómez-Luna, Eladio Gutiérrez, Oscar G. Plata, Onur Mutlu:
Exploiting Near-Data Processing to Accelerate Time Series Analysis. 279-282 - Nika Mansouri-Ghiasi, Jisung Park, Harun Mustafa, Jeremie S. Kim, Ataberk Olgun, Arvid Gollwitzer, Damla Senol Cali, Can Firtina, Haiyu Mao, Nour Almadhoun Alserr, Rachata Ausavarungnirun, Nandita Vijaykumar, Mohammed Alser, Onur Mutlu:
GenStore: In-Storage Filtering of Genomic Data for High-Performance and Energy-Efficient Genome Analysis. 283-287 - Christina Giannoula, Ivan Fernandez, Juan Gómez-Luna, Nectarios Koziris, Georgios I. Goumas, Onur Mutlu:
SparseP: Efficient Sparse Matrix Vector Multiplication on Real Processing-In-Memory Architectures. 288-291 - Juan Gómez-Luna, Yuxin Guo, Sylvan Brocard, Julien Legriel, Remy Cimadomo, Geraldo F. Oliveira, Gagandeep Singh, Onur Mutlu:
Machine Learning Training on a Real Processing-in-Memory System. 292-295 - Jiangwei Zhang, Chong Wang, Yi Cai, Zhenhua Zhu, Donald Kline, Huazhong Yang, Yu Wang:
WESCO: Weight-encoded Reliability and Security Co-design for In-memory Computing Systems. 296-301 - James Read, Wantong Li, Shimeng Yu:
A Method for Reverse Engineering Neural Network Parameters from Compute-in-Memory Accelerators. 302-307 - Nikhil Rangarajan, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf, Shubham Rai, Gopal Raut, Heba Abunahla, Baker Mohammad, Santosh Kumar Vishvakarma, Akash Kumar, Johann Knechtel, Ozgur Sinanoglu:
SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture. 308-313 - Farhad Merchant:
Security as an Important Ingredient in Neuromorphic Engineering. 314-319 - Lei Zhao, Youtao Zhang, Jun Yang:
A DNN Protection Solution for PIM accelerators with Model Compression. 320-325 - Alberto Bosio, Bastien Deveautour, Ian O'Connor:
Exploiting Approximate Computing for Efficient and Reliable Convolutional Neural Networks. 326 - Fernando Fernandes dos Santos, Paolo Rech, Angeliki Kritikakou, Olivier Sentieys:
Evaluating the Impact of Mixed-Precision on Fault Propagation for Deep Neural Networks on GPUs. 327 - Nima TaheriNejad, Salar Shakibhamedan:
Energy-aware Adaptive Approximate Computing for Deep Learning Applications. 328 - Ayush Arunachalam, Shamik Kundu, Arnab Raha, Suvadeep Banerjee, Kanad Basu:
Fault Resilience of DNN Accelerators for Compressed Sensor Inputs. 329-332 - Arjun Chaudhuri, Jonti Talukdar, Krishnendu Chakrabarty:
Probabilistic Fault Grading for AI Accelerators using Neural Twins. 333-338 - Mohammad Walid Charrwi, Huy Phan, Bo Yuan, Samah Mohamed Saeed:
Towards Yield Improvement for AI Accelerators: Analysis and Exploration. 339-344 - Fanruo Meng, Chengmo Yang:
Exploring Image Selection for Self-Testing in Neural Network Accelerators. 345-350 - Yawen Wu, Jingtong Hu:
Towards Independent On-device Artificial Intelligence. 351 - Junhuan Yang, Venkat Kalyan Reddy Yasa, Yi Sheng, Dayane Reis, Xun Jiao, Weiwen Jiang, Lei Yang:
Hardware-aware Automated Architecture Search for Brain-inspired Hyperdimensional Computing. 352-357 - Qing Lu, Weiwen Jiang, Meng Jiang, Jingtong Hu, Yiyu Shi:
Hardware/Software Co-Exploration for Graph Neural Architectures on FPGAs. 358-362 - Evanthia Faliagka, Christos Panagiotou, Christos P. Antonopoulos, Georgios Keramidas, Nikolaos S. Voros:
A Novel Marketplace Perspective Promoting Customized Low Energy Computing and IoT: The SMART4ALL Approach. 363-368 - Tobias Dörr, Florian Schade, Leonard Masing, Jürgen Becker, Georgios Keramidas, Christos P. Antonopoulos, Michail Mavropoulos, Vasilios I. Kelefouras, Nikolaos S. Voros:
Safety by Construction: Pattern-Based Application of Safety Mechanisms in XANDAR. 369-370 - Tim Hotfilter, Fabian Kreß, Fabian Kempf, Jürgen Becker, Imen Baili:
Data Movement Reduction for DNN Accelerators: Enabling Dynamic Quantization Through an eFPGA. 371-372 - Yu Wang, Shulin Zeng, Kaiyuan Guo, Xuefei Ning, Yali Zhao, Zhongyuan Qiu, Changcheng Tang, Shuang Liang, Huazhong Yang:
Efficient Autonomous Driving System Design: From Software to Hardware. 373-375 - Muhammed Ceylan Morgül, Xinfei Guo, Mircea Stan:
Towards Everlasting Flash: Preventing Permanent Flash Cell Damage using Circadian Rhythms. 376-379 - Paul-Antoine Matrangolo, Cédric Marchand, David Navarro, Ian O'Connor:
Hardware Emulation of FeFET On FPGA. 380-385 - Amir Ali Pour, Fatemeh Afghah, David Hély, Vincent Beroulle, Giorgio Di Natale:
Secure PUF-based Authentication and Key Exchange Protocol using Machine Learning. 386-389 - Taisei Ichikawa, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi:
Optoelectronic Implementation of Compact and Power-efficient Recurrent Neural Networks. 390-393 - Raghunandana K. K, B. K. S. V. L. Varaprasad, Matteo Sonza Reorda, Virendra Singh:
REFU: Redundant Execution with Idle Functional Units, Fault Tolerant GPGPU architecture. 394-397 - Michael Rogenmoser, Nils Wistoff, Pirmin Vogel, Frank K. Gürkaynak, Luca Benini:
On-Demand Redundancy Grouping: Selectable Soft-Error Tolerance for a Multicore Cluster. 398-401 - Amirmohammad Biuki, Naser Mohammadzadeh, Robert Wille, Sahar Sargaran:
Exact Mapping of Quantum Circuit Partitions to Building Blocks of the SAQIP Architecture. 402-405 - Eduarde D. Brandão, Joao P. Nespolo, Renato D. Peralta, Paulo F. Butzen, André Inácio Reis:
Possible Reductions to Generate circuits from BDDs. 406-409 - Binjing Li, Siyuan Lu, Keli Xie, Zhongfeng Wang:
Accelerating NLP Tasks on FPGA with Compressed BERT and a Hardware-Oriented Early Exit Method. 410-413 - Md. Najrul Islam, Rahul Shrestha, Shubhajit Roy Chowdhury:
A New Hardware-Efficient VLSI-Architecture of GoogLeNet CNN-Model Based Hardware Accelerator for Edge Computing Applications. 414-417 - Yu Zhuang, Gaoxiang Li, Khalid T. Mursi:
A Permutation Challenge Input Interface for Arbiter PUF Variants Against Machine Learning Attacks. 418-421 - Shivani Maurya, Ziaul Choudhury, Suresh Purini:
Accuracy Configurable FPGA Implementation of Harris Corner Detection. 422-427 - Abhijit Das, John Jose:
Designing Data-Aware Network-on-Chip for Performance. 428-433 - Qazi Arbab Ahmed, Marco Platzner:
On the Detection and Circumvention of Bitstream-level Trojans in FPGAs. 434-439 - Haroon Waris, Chenghua Wang, Weiqiang Liu:
Architectural-Space Exploration of Energy-Efficient Approximate Arithmetic Units for Error-Tolerant Applications. 440-445 - Renan C. A. Alves, Bruno C. Albertini, Marcos A. Simplício Jr.:
Securing hard drives with the Security Protocol and Data Model (SPDM). 446-447 - Laavanya Rachakonda, Daniel T. Marchand:
Fall-Sense: An Enhanced Sensor System to Predict and Detect Elderly Falls using IoMT. 448-449 - Joseph Clark, Himanshu Thapliyal, Travis S. Humble:
A Novel Approach to Quantum Circuit Partitioning. 450-451 - Pintu Kumar Sadhu, Venkata P. Yanambaka:
MC- PUF: A Robust Lightweight Controlled Physical Unclonable Function for Resource Constrained Environments. 452-453
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