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2020 – today
- 2024
[c5]Ming-Chieh Huang, Wei Wing Mar, Shankar Kanade, Boris Bai, Aditya Gayatri, Krishna Khairnar, Amy Lai, Yu-Hao Hsu, Hung-Jen Liao, Yih Wang, Tsung-Yung Jonathan Chang:
A 3.3GHz 1024X640 Multi-Bank Single-Port SRAM with Frequency Enhancing Techniques and 0.55V-1.35V Wide Voltage Range Operation in 3nm FinFET for HPC Applications. VLSI Technology and Circuits 2024: 1-2- 2023
- [j2]Kuen-Suan Chen, Yuan-Lung Lai, Ming-Chieh Huang, Tsang-Chuan Chang
:
Fuzzy judgement model for assessment of improvement effectiveness to performance of processing characteristics. Int. J. Prod. Res. 61(5): 1591-1605 (2023)
2010 – 2019
- 2019
- [c4]Dirk Pfaff, Shahaboddin Moazzeni, Leisheng Gao, Mei-Chen Chuang, Xin-Jie Wang, Chai Palusa, Robert Abbott, Rolando Ramirez, Maher Amer, Ming-Chieh Huang, Chih-Chang Lin, Fred Kuo, Wei-Li Chen, Tae Young Goh, Kenny Hsieh:
A 56Gb/s Long Reach Fully Adaptive Wireline PAM-4 Transceiver in 7nm FinFET. VLSI Circuits 2019: 270- - 2014
- [c3]Tsung-Ching Huang, Tao-Wen Chung, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin, Fu-Lung Hsueh:
8.4 A 28Gb/s 1pJ/b shared-inductor optical receiver with 56% chip-area reduction in 28nm CMOS. ISSCC 2014: 144-145 - 2012
- [c2]Tao-Wen Chung, Tsung-Ching Huang, S. Chung, Ming-Chieh Huang, Chih-Chang Lin, Chan-Hong Chern, Fu-Lung Hsueh:
A 2.7GHz 3.9mW Mesh-BJT LC-VCO with -204dBc/Hz FOM in 65nm CMOS. CICC 2012: 1-4 - [c1]Peter Kuoyuan Hsu, Yukit Tang, Derek Tao, Ming-Chieh Huang, Min-Jer Wang, C. H. Wu, Quincy Lee:
A SRAM cell array with adaptive leakage reduction scheme for data retention in 28nm high-k metal-gate CMOS. VLSIC 2012: 62-63
2000 – 2009
- 2003
- [j1]Tzu-Ming Yeh, Ming-Chieh Huang, Chi-Tsung Huang:
Estimate of process compositions and plantwide control from multiple secondary measurements using artificial neural networks. Comput. Chem. Eng. 27(1): 55-72 (2003)
Coauthor Index
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