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2020 – today
- 2024
[c13]Yuefeng Cao
, Minglei Zhang, Yan Zhu, Rui Paulo Martins, Chi-Hang Chan:
22.1 A 12GS/s 12b 4× Time-Interleaved Pipelined ADC with Comprehensive Calibration of TI Errors and Linearized Input Buffer. ISSCC 2024: 388-390- 2023
- [c12]Xiang-Hui Pan, Buhui Rui, Yuefeng Cao, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins:
A 12b 1GS/s ADC with Lightweight Input Buffer Distortion Background Calibration Achieving >75dB SFDR over PVT. CICC 2023: 1-2 - [c11]Yuefeng Cao, Minglei Zhang, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins:
A Single-Channel 12b 2GS/s PVT-Robust Pipelined ADC with Critically Damped Ring Amplifier and Time-Domain Quantizer. ISSCC 2023: 170-171 - [c10]Minglei Zhang, Yuefeng Cao, Yan Zhu, Chi-Hang Chan, Rui Paulo Martins:
A 79.5dB-SNDR Pipelined-SAR ADC with a Linearity-Shifting 32× Dynamic Amplifier and Mounted-Over-Die Bypass Capacitors. VLSI Technology and Circuits 2023: 1-2 - 2021
- [j1]Yuefeng Cao, Shumin Zhang, Tianli Zhang, Yongzhen Chen, Yutong Zhao, Chixiao Chen, Fan Ye, Junyan Ren:
A 91.0-dB SFDR Single-Coarse Dual-Fine Pipelined-SAR ADC With Split-Based Background Calibration in 28-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 68(2): 641-654 (2021)
2010 – 2019
- 2019
- [c9]Shumin Zhang, Yuefeng Cao, Fan Ye, Junyan Ren:
A 10b 250MS/s SAR ADC with Speed-Enhanced SAR Logic and Free Time More Than a Half of Sampling Period. ASICON 2019: 1-4 - [c8]Tianli Zhang, Yuefeng Cao, Shumin Zhang, Chixiao Chen, Fan Ye, Junyan Ren:
Machine Learning Based Prior-Knowledge-Free Calibration for Split Pipelined-SAR ADCs with Open-Loop Amplifiers Achieving 93.7-dB SFDR. ESSCIRC 2019: 189-192 - 2018
- [c7]Yuefeng Cao, Yongzhen Chen, Zhekan Ni, Fan Ye, Junyan Ren:
An 11b 80MS/s SAR ADC With Speed-Enhanced SAR Logic and High-Linearity CDAC. APCCAS 2018: 18-21 - [c6]Yuefeng Cao, Tianli Zhang, Yongzhen Chen, Fan Ye, Junyan Ren:
An Operational Amplifier Assisted Input Buffer and An Improved Bootstrapped Switch for High-Speed and High-Resolution ADCs. ISCAS 2018: 1-5 - [c5]Yongzhen Chen, Zhekan Ni, Yuefeng Cao, Fan Ye, Junyan Ren:
A 800 MS/s, 12-Bit, Ringamp-Based SAR assisted Pipeline ADC with Gain Error Cancellation. ISCAS 2018: 1-4 - [c4]Tianli Zhang, Yuefeng Cao, Fan Ye, Junyan Ren:
Use Multilayer Perceptron in Calibrating Multistage Non-linearity of Split Pipelined-ADC. ISCAS 2018: 1-5 - 2017
- [c3]Fubiao Cao, Yongzhen Chen, Yuefeng Cao, Fan Ye, Junyan Ren:
A proved dither-injection method for memory effect in double sampling pipelined ADC. ASICON 2017: 754-757 - [c2]Yuefeng Cao, Yongzhen Chen, Tianli Zhang, Fan Ye, Junyan Ren:
An improved ring amplifier with process- and supply voltage-insensitive dead-zone. MWSCAS 2017: 811-814 - 2016
- [c1]Jingxian Qi, Yuefeng Cao, Jianhua Shi:
Bad Data Identification Based on Optimized Local Outlier Detection Algorithm. GRMSE (1) 2016: 203-212
Coauthor Index
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