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ORCIDChuanjin Richard Shi
Person information
- affiliation: University of Washington, Department of Electrical Engineering, Seattle, WA, USA
- affiliation: Fudan University, School of Microelectronics, China
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Journal Articles
- 2023
[j18]Yanhong Wang
, Zihao Zhao, Xu Jin, Haotian Zheng, Maohua Nie, Qiaosha Zou, Chuanjin Richard Shi:
AutoMap: Automatic Mapping of Neural Networks to Deep Learning Accelerators for Edge Devices. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(9): 2994-3006 (2023)- [j17]Yongchuan Dong, Qiaosha Zou, Chuanjin Richard Shi:
Augmenting aspect-level sentiment classification with distance-related local context input. J. Supercomput. 79(10): 11198-11217 (2023) - [j16]Yanhong Wang, Tianchan Guan, Dimin Niu, Qiaosha Zou, Hongzhong Zheng, Chuanjin Richard Shi, Yuan Xie:
Accelerating Distributed GNN Training by Codes. IEEE Trans. Parallel Distributed Syst. 34(9): 2598-2614 (2023) - 2022
- [j15]Rongjin Xu, Dawei Ye, Chuanjin Richard Shi:
A 2.0-2.9 GHz ring-based injection-locked clock multiplier using a self-alignment frequency-tracking loop for reference spur reduction. Integr. 84: 1-11 (2022) - [j14]Dawei Ye, Rongjin Xu, Chuanjin Richard Shi:
Erratum to "A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain". IEEE J. Solid State Circuits 57(2): 671 (2022) - [j13]Rongjin Xu, Dawei Ye, Chuanjin Richard Shi:
Analysis and Design of Digital Injection-Locked Clock Multipliers Using Bang-Bang Phase Detectors. IEEE Trans. Circuits Syst. I Regul. Pap. 69(7): 2832-2844 (2022) - 2021
- [j12]Dawei Ye, Rongjin Xu, Chuanjin Richard Shi:
A Nonlinear Receiver Leveraging Cascaded Inverter-Based Envelope-Biased LNAs for In-Band Interference Suppression in the Amplitude Domain. IEEE J. Solid State Circuits 56(11): 3360-3374 (2021) - [j11]Chang Liu, Chuanjin Richard Shi:
Design of the Class-E Power Amplifier Considering the Temperature Effect of the Transistor On-Resistance for Sensor Applications. IEEE Trans. Circuits Syst. II Express Briefs 68(5): 1705-1709 (2021) - 2020
- [j10]Luis E. Tollinche, Richard Shi, Margaret Hannum, Patrick J. McCormick, Alisa Thorne, Kay See Tan, Gloria Yang, Meghana Mehta, Cindy B. Yeoh:
The impact of real-time clinical alerts on the compliance of anesthesia documentation: A retrospective observational study. Comput. Methods Programs Biomed. 191: 105399 (2020) - [j9]Haozhe Zhu, Chixiao Chen, Shiwei Liu, Qiaosha Zou, Mingyu Wang, Lihua Zhang, Xiaoyang Zeng, Chuanjin Richard Shi:
A Communication-Aware DNN Accelerator on ImageNet Using In-Memory Entry-Counting Based Algorithm-Circuit-Architecture Co-Design in 65-nm CMOS. IEEE J. Emerg. Sel. Topics Circuits Syst. 10(3): 283-294 (2020) - [j8]Liangjian Lyu, Yu Wang, Chixiao Chen, Chuanjin Richard Shi:
A 0.6V 1.07 μW/Channel neural interface IC using level-shifted feedback. Integr. 70: 51-59 (2020) - [j7]Dawei Ye, Yu Wang, Yingfei Xiang, Liangjian Lyu, Hao Min, Chuanjin Richard Shi:
A Wireless Power and Data Transfer Receiver Achieving 75.4% Effective Power Conversion Efficiency and Supporting 0.1% Modulation Depth for ASK Demodulation. IEEE J. Solid State Circuits 55(5): 1386-1400 (2020) - [j6]Liangjian Lyu, Dawei Ye, Chuanjin Richard Shi:
A 340 nW/Channel 110 dB PSRR Neural Recording Analog Front-End Using Replica-Biasing LNA, Level-Shifter Assisted PGA, and Averaged LFP Servo Loop in 65 nm CMOS. IEEE Trans. Biomed. Circuits Syst. 14(4): 811-824 (2020) - [j5]Liangjian Lyu, Dawei Ye, Rongjin Xu, Geng Mu, Heng Zhao, Yingfei Xiang, Yuting Tu, Yiyun Zhang, Chuanjin Richard Shi:
A Fully-Integrated 64-Channel Wireless Neural Interfacing SoC Achieving 110 dB AFE PSRR and Supporting 54 Mb/s Symbol Rate, Meter-Range Wireless Data Transmission. IEEE Trans. Circuits Syst. II Express Briefs 67-II(5): 831-835 (2020) - [j4]Aili Wang, Chuanjin Richard Shi:
Analysis of Passive Charge Sharing-Based Segmented SAR ADCs. IEEE Trans. Very Large Scale Integr. Syst. 28(5): 1195-1206 (2020) - 2019
- [j3]Chuanjin Richard Shi, Aili Wang:
Analysis of Bitwise and Samplewise Switched Passive Charge Sharing SAR ADCs. IEEE Trans. Very Large Scale Integr. Syst. 27(9): 1977-1989 (2019) - 2018
- [j2]Aili Wang, Chuanjin Richard Shi:
A 10-bit 50-MS/s SAR ADC with 1 fJ/Conversion in 14 nm SOI FinFET CMOS. Integr. 62: 246-257 (2018) - 2017
- [j1]Aili Wang, Chixiao Chen, Chuanjin Richard Shi:
Design and Analysis of an Always-ON Input-Biased pA-Current Sub-nW mV-Threshold Hysteretic Comparator for Near-Zero Energy Sensing. IEEE Trans. Circuits Syst. I Regul. Pap. 64-I(9): 2284-2294 (2017)
Conference and Workshop Papers
- 2023
- [c20]Renze Gan, Liangjian Lyu, Chuanjin Richard Shi:
A 7-Channel Bio-Signal Analog Front End Employing Single-End Chopping Amplifier Achieving 1.48 NEF. ESSCIRC 2023: 5-8 - 2022
- [c19]Renze Gan, Liangjian Lyu, Geng Mu, Chuanjin Richard Shi:
A Neural Recording Analog Front-End with Exponentially Tunable Pseudo Resistors and On-Chip Digital Frequency Calibration Loop Achieving 3.4% Deviation of High-Pass Cutoff Frequency in 5-to-500 Hz Range. CICC 2022: 1-2 - [c18]Rongjin Xu, Dawei Ye, Sirou Li, Chuanjin Richard Shi:
A 0.021mm2 65nm CMOS 2.5GHz Digital Injection-Locked Clock Multiplier with Injection Pulse Shaping Achieving -79dBc Reference Spur and 0.496mW/GHz Power Efficiency. ISSCC 2022: 214-216 - 2021
- [c17]Dawei Ye, Yuting Tu, Wenjun Gong, Rongjin Xu, Chuanjin Richard Shi:
A Two-Tone Wake-Up Receiver with an Envelope-Detector-First Architecture Using Envelope Biasing and Active Inductor Load Achieving 41/33dB In-Band Rejection to CW/AM Interference. A-SSCC 2021: 1-3 - [c16]Geng Mu, Dawei Ye, Liangjian Lyu, Xiaobin Zhao, Chuanjin Richard Shi:
An 8-Channel Analog Front-End with a PVT-lnsensitive Switched-Capacitor and Analog Combo DC Servo Loop Achieving 300mV Tolerance and 0.64s Recovery Time to Electrode-DC Offset for Physiological Signal Recording. CICC 2021: 1-2 - 2020
- [c15]Yuting Tu, Rongjin Xu, Dawei Ye, Liangjian Lyu, Chuanjin Richard Shi:
A 400 MHz, 8-Bit, 1.75-ps Resolution Pipelined-Two-Step Time-to-Digital Converter with Dynamic Time Amplification. ISCAS 2020: 1-4 - 2019
- [c14]Liangjian Lyu, Yu Wang, Chixiao Chen, Chuanjin Richard Shi:
A low-voltage low-power multi-channel neural interface IC using level-shifted feedback technology. ASP-DAC 2019: 13-14 - [c13]Aili Wang, Chixiao Chen, Chuanjin Richard Shi:
A 9-bit Resistor-Based All-Digital Temperature Sensor with a SAR-Quantization Embedded Differential Low-Pass Filter in 65nm CMOS Consuming 57pJ with a 2.5 μs Conversion Time. CICC 2019: 1-4 - [c12]Liangjian Lyu, Dawei Ye, Chuanjin Richard Shi:
A 340nW/Channel Neural Recording Analog Front-End using Replica-Biasing LNAs to Tolerate 200mVpp Interfere from 350mV Power Supply. ISCAS 2019: 1-4 - [c11]Dawei Ye, Rongjin Xu, Liangjian Lyu, Chuanjin Richard Shi:
A 2.46GHz, -88dBm Sensitivity CMOS Passive Mixer-First Nonlinear Receiver with >50dB Tolerance to In-Band Interferer. ISCAS 2019: 1-4 - [c10]Dawei Ye, Rongjin Xu, Chuanjin Richard Shi:
A 2.4GHz 65nm CMOS Mixer-First Receiver Using 4-Stage Cascaded Inverter-Based Envelope-Biased LNAs Achieving 66dB In-Band Interference Tolerance and -83dBm Sensitivity. ISSCC 2019: 414-416 - 2018
- [c9]Ailing Piao, Aili Wang, Chuanjin Richard Shi:
Pin-Efficient 12-Bit 8-Wire 8-Level Permutation Coding for High-Speed Parallel Wireline Tranceivers. ISCAS 2018: 1-4 - [c8]Yu Wang, Dawei Ye, Liangjian Lyu, Yingfei Xiang, Hao Min, Chuanjin Richard Shi:
A 13.56MHz Wireless Power and Data Transfer Receiver Achieving 75.4% Effective-Power-Conversion Efficiency with 0.1% ASK Modulation Depth and 9.2mW Output Power. ISSCC 2018: 142-144 - [c7]Marcel Urban, Sachin S. Sapatnekar, Richard Shi:
Plenaries. SMACD 2018: 1-2 - 2016
- [c6]Allen Waters, Aili Wang, Chuanjin Richard Shi:
Highly time-interleaved noise-shaped SAR ADC with reconfigurable order. ISCAS 2016: 1026-1029 - [c5]Aili Wang, Allen Waters, Chuanjin Richard Shi:
A sub-nW mV-range programmable threshold comparator for near-zero-energy sensing. ISCAS 2016: 1054-1057 - 2013
- [c4]Xinmiao Zhang, Richard Shi, James A. Ritcey:
Reducing the latency of Lee-O'Sullivan interpolation through modified initialization. ITA 2013: 1-5 - 2012
- [c3]Xinmiao Zhang, Fang Cai, Richard Shi:
Low-power LDPC decoding based on iteration prediction. ISCAS 2012: 3041-3044 - [c2]Xinmiao Zhang, Richard Shi, James A. Ritcey:
On the implementation of modified fuzzy vault for biometric encryption. ITA 2012: 56-61 - 2010
- [c1]Chuanjin Richard Shi:
Mixed-signal system-on-chip verification using a recursively-verifying-modeling (RVM) methodology. ISCAS 2010: 1432-1435
Informal and Other Publications
- 2023
- [i1]Huwan Peng, Scott Davidson, Richard Shi, Shuaiwen Leon Song, Michael B. Taylor:
Chiplet Cloud: Building AI Supercomputers for Serving Large Generative Language Models. CoRR abs/2307.02666 (2023)
Coauthor Index
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