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2000 – 2009
- 2007
[j3]Yuanbin Guo, Jianzhong Zhang, Dennis McCain, Joseph R. Cavallaro:
Structured Parallel Architecture for Displacement MIMO Kalman Equalizer in CDMA Systems. IEEE Trans. Circuits Syst. II Express Briefs 54-II(2): 122-126 (2007)- 2006
- [j2]Yuanbin Guo, Jianzhong (Charlie) Zhang, Dennis McCain, Joseph R. Cavallaro
:
An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture. EURASIP J. Adv. Signal Process. 2006 (2006) - [j1]Yuanbin Guo, Dennis McCain, Joseph R. Cavallaro, Andres Takach:
Rapid Industrial Prototyping and SoC Design of 3G/4G Wireless Systems Using an HLS Methodology. EURASIP J. Embed. Syst. 2006 (2006) - [c9]Tejas M. Bhatt, Vishwas Sundaramurthy, Victor Stolpman, Dennis McCain:
Pipelined Block-Serial Decoder Architecture for Structured Ldpc Codes. ICASSP (4) 2006: 225-228 - [c8]Yuanbin Guo, Dennis McCain:
Rapid prototyping and VLSI exploration for 3g/4G MIMO wireless systems using integrated catapult-c methodology. WCNC 2006: 958-963 - 2005
- [c7]Tejas M. Bhatt, Dennis McCain:
Matlab as a development environment for FPGA design. DAC 2005: 607-610 - [c6]Yuanbin Guo, Dennis McCain:
Reduced QRD-M detector in MIMO-OFDM systems with partial and embedded sorting. GLOBECOM 2005: 6 - [c5]Yuanbin Guo, Jianzhong (Charlie) Zhang, Dennis McCain, Joseph R. Cavallaro:
Displacement MIMO Kalman equalizer for CDMA downlink in fast fading channels. GLOBECOM 2005: 6 - [c4]Yuanbin Guo, Dennis McCain, Joseph R. Cavallaro:
FFT-accelerated iterative MIMO chip equalizer architecture for CDMA downlink. ICASSP (3) 2005: 1005-1008 - 2004
- [c3]Yuanbin Guo, Jianzhong (Charlie) Zhang, Dennis McCain, Joseph R. Cavallaro:
Efficient MIMO equalization for downlink multi-code CDMA: complexity optimization and comparative study. GLOBECOM 2004: 2513-2519 - [c2]Yuanbin Guo, Dennis McCain, Joseph R. Cavallaro:
Low complexity System-on-Chip architectures of Parallel-Residue-Compensation in CDMA systems. ISCAS (4) 2004: 77-80 - 2003
- [c1]Yuanbin Guo, Gang Xu, Dennis McCain, Joseph R. Cavallaro:
Rapid Scheduling of Efficient VLSI Architectures for Next-Generation HSDPA. IEEE International Workshop on Rapid System Prototyping 2003: 179-185
Coauthor Index
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