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ORCID42nd DAC 2005: San Diego, CA, USA
- William H. Joyner Jr., Grant Martin, Andrew B. Kahng:
Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005. ACM 2005, ISBN 1-59593-058-2
Panel
- Jay Vleeschhouwer, Warren East, Michael J. Fister, Aart J. de Geus, Walden C. Rhines, Jackson Hu, Rick Cassidy:
Differentiate and deliver: leveraging your partners. 1
Error-tolerant design
- Subhasish Mitra, Tanay Karnik, Norbert Seifert, Ming Zhang:
Logic soft errors in sub-65nm technologies design and CAD challenges. 2-4 - William Heidergott:
SEU tolerant device, circuit and processor design. 5-10
Microarchitecture-level power analysis and optimization techniques
- Diana Marculescu
, Emil Talpes:
Variability and energy awareness: a microarchitecture-level perspective. 11-16 - Peter Petrov, Daniel Tracy, Alex Orailoglu:
Energy-effcient physically tagged caches for embedded processors with virtual memory. 17-22 - Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Hybrid simulation for embedded software energy estimation. 23-26 - Patrick Schaumont, Bo-Cheng Charles Lai, Wei Qin, Ingrid Verbauwhede:
Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable design. 27-30
Leakage analysis and optimization
- Feng Gao, John P. Hayes:
Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages. 31-36 - Afshin Abdollahi, Farzan Fallah, Massoud Pedram:
An effective power mode transition technique in MTCMOS circuits. 37-42 - Nikhil Jayakumar, Sandeep Dhar, Sunil P. Khatri:
A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents. 43-46 - Lin Yuan, Gang Qu:
Enhanced leakage reduction Technique by gate replacement. 47-50
Analog macromodeling
- Ning Dong, Jaijeet S. Roychowdhury:
Automated nonlinear Macromodelling of output buffers for high-speed digital applications. 51-56 - Ying Wei, Alex Doboli:
Systematic development of analog circuit structural macromodels through behavioral model decoupling. 57-62 - Mengmeng Ding, Ranga Vemuri:
A combined feasibility and performance macromodel for analog circuits. 63-68
Panel
- Francine Bacchini, David Maliniak, Terry Doherty, Peter McShane, Suhas A. Pai, Sriram Sundararajan, Soo-Kwan Eo, Pascal Urard:
ESL: building the bridge between systems to silicon. 69-70
Statistical timing analysis
- Hongliang Chang, Vladimir Zolotov, Sambasivan Narayan, Chandu Visweswariah:
Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions. 71-76 - Yaping Zhan, Andrzej J. Strojwas, Xin Li, Lawrence T. Pileggi, David Newmark, Mahesh Sharma:
Correlation-aware statistical timing analysis with non-gaussian delay distributions. 77-82 - Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner, Charlie Chung-Ping Chen:
Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model. 83-88 - Vishal Khandelwal, Ankur Srivastava:
A general framework for accurate statistical timing analysis considering correlations. 89-94
Embedded software
- Feihui Li, Mahmut T. Kandemir:
Locality-conscious workload assignment for array-based computations in MPSOC architectures. 95-100 - Stefan Valentin Gheorghita, Sander Stuijk, Twan Basten, Henk Corporaal:
Automatic scenario detection for improved WCET estimation. 101-104 - Jungeun Kim, Taewhan Kim:
Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design. 105-110 - Ravindra Jejurikar, Rajesh K. Gupta:
Dynamic slack reclamation with procrastination scheduling in real-time embedded systems. 111-116
Advances in design-for-testability methods
- Erik H. Volkerink, Subhasish Mitra:
Response compaction with any number of unknowns using a new LFSR architecture. 117-122 - Qiang Xu, Nicola Nicolici, Krishnendu Chakrabarty:
Multi-frequency wrapper design and optimization for embedded cores under average power constraints. 123-128 - Irith Pomeranz:
N-detection under transparent-scan. 129-134 - Bo Yang, Kaijie Wu, Ramesh Karri:
Secure scan: a design-for-test architecture for crypto chips. 135-140
Advances in boundary element methods for parasitic extraction
- Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram:
A green function-based parasitic extraction method for inhomogeneous substrate layers. 141-146 - Xin Hu, Jung Hoon Lee, Jacob White, Luca Daniel:
Analysis of full-wave conductor system impedance over substrate using novel integration techniques. 147-152 - Michael W. Beattie, Hui Zheng, Anirudh Devgan, Byron Krauter:
Spatially distributed 3D circuit models. 153-158 - Dipanjan Gope, Indranil Chowdhury, Vikram Jandhyala:
DiMES: multilevel fast direct solver based on multipole expansions for parasitic extraction of massively coupled 3D microelectronic structures. 159-162 - Rong Jiang, Yi-Hao Chang, Charlie Chung-Ping Chen:
ICCAP: a linear time sparse transformation and reordering algorithm for 3D BEM capacitance extraction. 163-166
Management Day Session
- Dennis Wassung, Yervant Zorian, Magdy S. Abadir, Mark Bapst, Colin Harris:
Choosing flows and methodologies for SoC design. 167
Panel
- Naveed A. Sherwani, Susan Lippincott Mack, Alex Alexanian, Premal Buch, Carlo Guardiani, Harold Lehon, Peter Rabkin, Atul Sharan:
DFM rules! 168-169 - Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong:
Partitioning-based approach to fast on-chip decap budgeting and minimization. 170-175 - Yongqiang Lu, Cliff C. N. Sze, Xianlong Hong, Qiang Zhou, Yici Cai, Liang Huang, Jiang Hu:
Navigating registers in placement for clock network minimization. 176-181 - Yow-Tyng Nieh, Shih-Hsu Huang, Sheng-Yu Hsu:
Minimizing peak current via opposite-phase clock tree. 182-185 - Haihua Su, David Widiger, Chandramouli V. Kashyap, Frank Liu, Byron Krauter:
A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis. 186-189 - Chong Zhao, Yi Zhao, Sujit Dey:
Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits. 190-195
Physical considerations in high-level synthesis
- Rajarshi Mukherjee, Seda Ogrenci Memik, Gokhan Memik:
Temperature-aware resource allocation and binding in high-level synthesis. 196-201 - Xiaoyong Tang, Hai Zhou, Prithviraj Banerjee:
Leakage power optimization with dual-Vth library in high-level synthesis. 202-207 - Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Zhou:
Incremental exploration of the combined physical and behavioral design space. 208-213 - Mohsen Saneei, Ali Afzali-Kusha, Zainalabedin Navabi:
Sign bit reduction encoding for low power applications. 214-217 - Tingyuan Nie, Tomoo Kisaka, Masahiko Toyonaga:
A watermarking system for IP protection by a post layout incremental router. 218-221
Architectures for cryptography and security applications
- Kris Tiri, David D. Hwang, Alireza Hodjat, Bo-Cheng Lai, Shenglin Yang, Patrick Schaumont, Ingrid Verbauwhede:
A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing. 222-227 - Kris Tiri, Ingrid Verbauwhede:
Simulation models for side-channel information leaks. 228-233 - Young H. Cho, William H. Mangione-Smith:
A pattern matching coprocessor for network security. 234-239 - Tomás Balderas-Contreras, René Cumplido:
High performance encryption cores for 3G networks. 240-243 - Pallav Gupta, Srivaths Ravi, Anand Raghunathan, Niraj K. Jha:
Efficient fingerprint-based user authentication for embedded systems. 244-247
Performance, energy, and fault-tolerance considerations for MPSoC designs
- Yanhong Liu, Samarjit Chakraborty, Wei Tsang Ooi:
Approximate VCCs: a new characterization of multimedia workloads for system-level MpSoC design. 248-253 - Christian Sauer, Matthias Gries, Sören Sonntag:
Modular domain-specific implementation and exploration framework for embedded software platforms. 254-259 - Xi Chen, Abhijit Davare, Harry Hsieh, Alberto L. Sangiovanni-Vincentelli, Yosinori Watanabe:
Simulation based deadlock analysis for system level designs. 260-265 - Sorin Manolache, Petru Eles, Zebo Peng:
Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC. 266-269 - Andrey V. Zykov, Elias Mizan, Margarida F. Jacome, Gustavo de Veciana, Ajay Subramanian:
High performance computing on fault-prone nanotechnologies: novel microarchitecture techniques exploiting reliability-delay trade-offs. 270-273
Management Day Session
- Nic Mokhoff, Yervant Zorian, Kamalesh N. Ruparel, Hao Nham, Francesco Pessolano, Kee Sup Kim:
How to determine the necessity for emerging solutions. 274-275
losing the power gap between ASIC and custom
- David G. Chinnery, Kurt Keutzer:
Closing the power gap between ASIC and custom: an ASIC perspective. 275-280 - Andrew Chang, William J. Dally:
Explaining the gap between ASIC and custom power: a custom perspective. 281-284 - Ruchir Puri, Leon Stok, Subhrajit Bhattacharya:
Keeping hot chips cool. 285-288
Panel
- Navraj Nandra, Phil Dworsky, Rick Merritt, John F. D'Ambrosia, Adam Healey, Boris Litinsky, John T. Stonick, Joe Abler:
Interconnects are moving from MHz->GHz should you be afraid?: or... "my giga hertz, does yours?". 289-290
Wireless session: information design methodology
- Jean-Samuel Chenard, Chun Yiu Chu, Zeljko Zilic, Milica Popovic:
Design methodology for wireless nodes with printed antennas. 291-296 - Yan Meng, Andrew P. Brown, Ronald A. Iltis, Timothy Sherwood, Hua Lee, Ryan Kastner:
MP core: algorithm and design techniques for efficient channel estimation in wireless applications. 297-302 - Wolfgang Eberle, Bruno Bougard, Sofie Pollin, Francky Catthoor:
From myth to methodology: cross-layer design for energy-efficient wireless communication. 303-308
Statistical optimization and manufacturability
- Murari Mani, Anirudh Devgan, Michael Orshansky:
An efficient algorithm for statistical minimization of total power under timing yield constraints. 309-314 - Jaskirat Singh, Vidyasagar Nookala, Zhi-Quan Luo, Sachin S. Sapatnekar:
Robust gate sizing by geometric programming. 315-320 - Aseem Agarwal, Kaviraj Chopra, David T. Blaauw, Vladimir Zolotov:
Circuit optimization using statistical static timing analysis. 321-324 - Bor-Yiing Su, Yao-Wen Chang:
An exact jumper insertion algorithm for antenna effect avoidance/fixing. 325-328
Application specific architecture design tools
- Kingshuk Karuri, Mohammad Abdullah Al Faruque, Stefan Kraemer, Rainer Leupers, Gerd Ascheid, Heinrich Meyr:
Fine-grained application source code profiling for ASIP design. 329-334 - Sudarshan Banerjee, Elaheh Bozorgzadeh, Nikil D. Dutt:
Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration. 335-340 - Ho Young Kim, Tag Gon Kim:
Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse. 341-344 - Dohyung Kim, Youngmin Yi, Soonhoi Ha:
Trace-driven HW/SW cosimulation using virtual synchronization technique. 345-348
The Titanic: what went wrong!
- Sani R. Nassif, Paul S. Zuchowski, Claude Moughanni, Mohamed Moosa, Stephen D. Posluszny, Ward Vercruysse:
The Titanic: what went wrong! 349-350
Panel
- Francine Bacchini, Jan M. Rabaey, Allan Cox, Frank Lane, Rudy Lauwereins, Ulrich Ramacher, David Witt:
Wireless platforms: GOPS for cents and MilliWatts. 351-352
Design methods for manufacturability enhancements
- V. Kheterpal, Vyacheslav Rovner, T. G. Hersan, D. Motiani, Y. Takegawa, Andrzej J. Strojwas, Lawrence T. Pileggi:
Design methodology for IC manufacturability based on regular logic-bricks. 353-358 - Jie Yang, Luigi Capodieci, Dennis Sylvester:
Advanced timing analysis based on post-OPC extraction of critical dimensions. 359-364 - Puneet Gupta, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester:
Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions. 365-368 - Joydeep Mitra, Peng Yu, David Zhigang Pan:
RADAR: RET-aware detailed routing using fast lithography simulations. 369-372
Methods and representations for logic synthesis
- Tsutomu Sasao, Munehiro Matsuura:
BDD representation for incompletely specifiedvmultiple-output logic functions and its applications to functional decomposition. 373-378 - Afshin Abdollahi, Massoud Pedram:
A new canonical form for fast boolean matching in logic synthesis and verification. 379-384 - Xiao Yu Li, Matthias F. M. Stallmann, Franc Brglez:
Effective bounding techniques for solving unate and binate covering problems. 385-390
Generating efficient models for analog circuits
- Yayun Wan, Jaijeet S. Roychowdhury:
Operator-based model-order reduction of linear periodically time-varying systems. 391-396 - Vinita Vasudevan:
Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits. 397-402 - Saurabh K. Tiwary, Rob A. Rutenbar:
Scalable trajectory methods for on-demand analog macromodel extraction. 403-408
Special session: emerging directions in wireless
- William Krenik, Anuj Batra:
Cognitive radio techniques for wide area networks. 409-412 - Jeffrey M. Gilbert, Won-Joon Choi, Qinfang Sun:
MIMO technology for advanced wireless local area networks. 413-415 - Clark T.-C. Nguyen:
RF MEMS in wireless architectures. 416-420
CAD for FPGAs
- Paul Metzgen, Dominic Nancekievill:
Multiplexer restructuring for FPGA implementation cost reduction. 421-426 - Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown:
FPGA technology mapping: a study of optimality. 427-432 - Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown:
Incremental retiming for FPGA physical synthesis. 433-438 - Kenneth Eguro, Scott Hauck, Akshay Sharma:
Architecture-adaptive range limit windowing for simulated annealing FPGA placement. 439-444
Effective formal verification using word-level reasoning, bit-level generality, and parallelism
- Himanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke:
Word level predicate abstraction and refinement for verifying RTL verilog. 445-450 - Ganapathy Parthasarathy, Madhu K. Iyer, Kwang-Ting Cheng, Forrest Brewer:
Structural search for RTL with predicate learning. 451-456 - Markus Wedler, Dominik Stoffel, Wolfgang Kunz:
Normalization at the arithmetic bit level. 457-462 - Hari Mony, Jason Baumgartner, Viresh Paruthi, Robert Kanzelman:
Exploiting suspected redundancy without proving it. 463-466 - Debashis Sahoo, Jawahar Jain, Subramanian K. Iyer, David L. Dill, E. Allen Emerson:
Multi-threaded reachability. 467-470
Advances in synthesis
- Grace Nordin, Peter A. Milder, James C. Hoe, Markus Püschel:
Automatic generation of customized discrete fourier transform IPs. 471-474 - Shih-Hsu Huang, Yow-Tyng Nieh, Feng-Pin Lu:
Race-condition-aware clock skew scheduling. 475-478 - Swarup Bhunia, Nilanjan Banerjee, Qikai Chen, Hamid Mahmoodi-Meimand, Kaushik Roy:
A novel synthesis approach for active leakage power reduction using dynamic supply gating. 479-484 - Kundan Nepal, R. Iris Bahar, Joseph L. Mundy, William R. Patterson, Alexander Zaslavsky:
Designing logic circuits for probabilistic computation in the presence of noise. 485-490 - Peggy B. McGee, Steven M. Nowick:
A lattice-based framework for the classification and design of asynchronous pipelines. 491-496
Coping with buffering
- King Ho Tam, Lei He:
Power optimal dual-Vdd buffered tree considering buffer stations and blockages. 497-502 - Brent Goplen, Prashant Saxena, Sachin S. Sapatnekar:
Net weighting to reduce repeater counts during placement. 503-508 - Cliff C. N. Sze, Charles J. Alpert, Jiang Hu, Weiping Shi:
Path based buffer insertion. 509-514 - Haoxing Ren, David Zhigang Pan, Charles J. Alpert, Paul Villarrubia:
Diffusion-based placement migration. 515-520
Panel
- Francine Bacchini, Gabe Moretti, Harry Foster, Janick Bergeron, Masayuki Nakamura, Shrenik Mehta, Laurent Ducousso:
Is methodology the highway out of verification hell? 521-522
Impact of process variations on power
- Hongliang Chang, Sachin S. Sapatnekar:
Full-chip analysis of leakage power under process variations, including spatial correlations. 523-528 - Navid Azizi, Muhammad M. Khellah, Vivek De, Farid N. Najm:
Variations-aware low-power design with voltage scaling. 529-534 - Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David T. Blaauw, Stephen W. Director:
Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance. 535-540 - Sarvesh Bhardwaj, Sarma B. K. Vrudhula:
Leakage minimization of nano-scale circuits in the presence of systematic and random variations. 541-546
Special session: The best of wireless at ISSCC
- Pascal Urard, L. Paumier, P. Georgelin, T. Michel, V. Lebars, E. Yeo, B. Gupta:
A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3). 547-548 - Philippe Royannez, Hugh Mair, Franck Dahan, Mike Wagner, Mark Streeter, Laurent Bouetel, Joel Blasquez, H. Clasen, G. Semino, Julie Dong, D. Scott, B. Pitts, Claudine Raibaut, Uming Ko:
A design platform for 90-nm leakage reduction techniques. 549-550 - Arun Natarajan, Abbas Komijani, Ali Hajimiri:
A 24 GHz phased-array transmitter in 0.18µm CMOS. 551-552
Architectural support for communication
- Taeweon Suh, Daehyun Kim, Hsien-Hsin S. Lee:
Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs. 553-558 - Jongman Kim, Dongkook Park, Theo Theocharides, Narayanan Vijaykrishnan, Chita R. Das:
A low latency router supporting adaptivity for on-chip interconnects. 559-564 - Sudeep Pasricha, Nikil D. Dutt, Elaheh Bozorgzadeh, Mohamed Ben-Romdhane:
Floorplan-aware automated synthesis of bus-based communication architectures. 565-570 - Krishna Sekar, Kanishka Lahiri, Anand Raghunathan, Sujit Dey:
FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology. 571-574 - Sven Heithecker, Rolf Ernst:
Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements. 575-578
New approaches to physical design problems
- Vidyasagar Nookala, Ying Chen, David J. Lilja, Sachin S. Sapatnekar:
Microarchitecture-aware floorplanning using a statistical design of experiments approach. 579-584 - Zhong Xiu, Rob A. Rutenbar:
Timing-driven placement by grid-warping. 585-591 - Ulrich Brenner, Markus Struzyna:
Faster and better global placement by a new transportation algorithm. 591-596