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ORCIDKimihiko Kato
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2020 – today
- 2024
[j3]Takumi Inaba, Hiroshi Oka, Hidehiro Asai, Hiroshi Fuketa, Shota Iizuka, Kimihiko Kato, Shunsuke Shitakata, Koichi Fukuda
, Takahiro Mori:
Temperature Dependent Variations of Low-Frequency Noise Sources in Cryogenic Short-Channel Bulk MOSFETs. IEEE Access 12: 12458-12464 (2024)- [c7]Shunsuke Shitakata, Hiroshi Oka, Kimihiko Kato, Takumi Inaba, Shota Iizuka, Hidehiro Asai, Takahiro Mori:
Occurrence and Mitigation of Hot Carrier Degradation in Cryogenic MOSFET Operation. DRC 2024: 1-2 - 2023
- [j2]Hiroshi Oka, Takumi Inaba, Shunsuke Shitakata, Kimihiko Kato, Shota Iizuka, Hidehiro Asai, Hiroshi Fuketa, Takahiro Mori:
Origin of Low-Frequency Noise in Si n-MOSFET at Cryogenic Temperatures: The Effect of Interface Quality. IEEE Access 11: 121567-121573 (2023) - [j1]Shimpei Nishiyama, Kimihiko Kato, Yongxun Liu, Raisei Mizokuchi, Jun Yoneda, Tetsuo Kodera, Takahiro Mori:
Single-Electron Transistor Operation of a Physically Defined Silicon Quantum Dot Device Fabricated by Electron Beam Lithography Employing a Negative-Tone Resist. IEICE Trans. Electron. 106(10): 592-596 (2023) - [c6]Takumi Inaba, Hiroshi Oka, Hidehiro Asai, Hiroshi Fuketa, Shota Iizuka, Kimihiko Kato, Shunsuke Shitakata, Koichi Fukuda, Takahiro Mori:
Determining the low-frequency noise source in cryogenic operation of short-channel bulk MOSFETs. VLSI Technology and Circuits 2023: 1-2 - 2022
- [c5]Hiroshi Oka, Takumi Inaba, Shota Iizuka, Hidehiro Asai, Kimihiko Kato, Takahiro Mori:
Effect of Conduction Band Edge States on Coulomb-Limiting Electron Mobility in Cryogenic MOSFET Operation. VLSI Technology and Circuits 2022: 334-335 - 2021
- [c4]Shota Iizuka, Kimihiko Kato, Atsushi Yagishita, Hidehiro Asai, Tetsuya Ueda, Hiroshi Oka, Junichi Hattori, Tsutomu Ikegami, Koichi Fukuda, Takahiro Mori:
Buried nanomagnet realizing high-speed/low-variability silicon spin qubits: implementable in error-correctable large-scale quantum computers. VLSI Circuits 2021: 1-2
2010 – 2019
- 2019
- [c3]Kei Sumita, Jun Takeyasu, Kimihiko Kato, Kasidit Toprasertpong, Mitsuru Takenaka, Shinichi Takagi:
Fabrication of High Quality InAs-on-Lnsulator Structures by Smart Cut Process with Reuse of InAs Wafers. 3DIC 2019: 1-2 - [c2]Shinichi Takagi, Kimihiko Kato, Kei Sumita, Kwangwon Jo, Cheol-Min Lim, Ryotaro Takaguchi, Dae-Hwan Ahn, Jun Takeyasu, Kasidit Toprasertpong, Mitsuru Takenaka:
Advanced MOS Device Technology for Low Power Logic LSI. MIXDES 2019: 26-33 - 2018
- [c1]Shinichi Takagi, Kimihiko Kato, Wu-Kang Kim, Kwangwon Jo, Ryo Matsumura, Ryotaro Takaguchi, Dae-Hwan Ahn, Takahiro Gotow, Mitsuru Takenaka:
MOS Device Technology using Alternative Channel Materials for Low Power Logic LSI. ESSDERC 2018: 6-11
Coauthor Index
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