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ORCIDV. Visvanathan
This is just a disambiguation page, and is not intended to be the bibliography of an actual person. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.
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2010 – 2019
- 2015
[j18]Neel Gala, V. R. Devanathan, V. Visvanathan, V. Kamakoti:
Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate Application Specific Integrated Chips Targeting Media-Based Applications. J. Low Power Electron. 11(2): 133-148 (2015)- 2014
- [c29]Neel Gala, V. R. Devanathan, Karthik Srinivasan, V. Visvanathan, V. Kamakoti:
ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICs. VLSID 2014: 342-347 - 2013
- [j17]Virat Gandhi, V. R. Devanathan, V. Visvanathan, Milan Patnaik
, V. Kamakoti:
Supply and Body-Bias Voltage Assignment Based Technique for Power and Temperature Control on a Chip at Iso-Performance Conditions. J. Low Power Electron. 9(2): 207-228 (2013) - 2012
- [j16]Rama Kumar Pasumarthi, V. R. Devanathan, V. Visvanathan, Seetal Potluri, V. Kamakoti:
Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCs. J. Low Power Electron. 8(5): 684-695 (2012) - 2010
- [j15]Janakiraman Viraraghavan, Bharadwaj Amrutur, V. Visvanathan:
Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(7): 1056-1069 (2010)
2000 – 2009
- 2008
- [j14]Janakiraman Viraraghavan, Bharadwaj Amrutur, V. Visvanathan:
Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor Stacks. J. Low Power Electron. 4(3): 301-319 (2008) - [c28]Bishnu Prasad Das, Bharadwaj Amrutur, H. S. Jamadagni, N. V. Arvind, V. Visvanathan:
Within-die gate delay variability measurement using re-configurable ring oscillator. CICC 2008: 133-136 - 2005
- [c27]Sreeram Chandrasekar, Gaurav Kumar Varshney, V. Visvanathan:
A Comprehensive Methodology for Noise Characterization of ASIC Cell Libraries. ISQED 2005: 530-535 - [c26]Sreeram Chandrasekar, V. Visvanathan, Gaurav Kumar Varshney:
Application of DC Transfer Characteristics in the Elimination of Redundant Vectors for Transient Noise Characterization of Static CMOS Circuits. VLSI Design 2005: 336-341 - [c25]B. Suresh, V. Visvanathan, R. S. Krishnan, H. S. Jamadagni:
Application of Alpha Power Law Models to PLL Design Methodology. VLSI Design 2005: 768-773 - 2001
- [j13]Pradip Mandal, V. Visvanathan:
CMOS op-amp sizing using a geometric programming formulation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(1): 22-38 (2001) - 2000
- [j12]S. Ramanathan, S. K. Nandy, V. Visvanathan:
Reconfigurable Filter Coprocessor Architecture for DSP Applications. J. VLSI Signal Process. 26(3): 333-359 (2000)
1990 – 1999
- 1999
- [j11]S. Ramanathan, V. Visvanathan:
Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay1. Integr. 27(1): 1-32 (1999) - [j10]S. Ramanathan, V. Visvanathan, S. K. Nandy:
Synthesis of ASIPs for DSP algorithms. Integr. 28(1): 13-32 (1999) - [j9]S. Ramanathan, V. Visvanathan, S. K. Nandy:
A computational engine for multirate FIR digital filtering. Signal Process. 79(2): 213-222 (1999) - [j8]S. Ramanathan, V. Visvanathan, S. K. Nandy:
Architectural Synthesis of Computational Engines for Subband Adaptive Filtering. J. VLSI Signal Process. 22(3): 173-195 (1999) - [c24]Avinash K. Gautam, V. Visvanathan, S. K. Nandy:
Automatic Generation of Tree Multipliers Using Placement-Driven Netlists. ICCD 1999: 285-288 - [c23]Pradip Mandal, V. Visvanathan:
A New Approach for CMOS Op-Amp Synthesis. VLSI Design 1999: 189-195 - [c22]S. Ramanathan, V. Visvanathan, S. K. Nandy:
Synthesis of Configurable Architectures for DSP Algorithms. VLSI Design 1999: 350-357 - 1997
- [c21]S. Ramanathan, V. Visvanathan:
Low-Power Configurable Processor Array for DLMS Adaptive Filtering. VLSI Design 1997: 198-207 - [c20]Pradip Mandal, V. Visvanathan:
A Self-Biased High Performance Folded Cascode CMOS Op-Amp. VLSI Design 1997: 429-434 - 1996
- [c19]A. Ratan Gupta, V. Visvanathan:
VLSI Implementation of DSP Architectures. VLSI Design 1996: 3 - [c18]Pradip Mandal, V. Visvanathan:
Design of high performance two stage CMOS cascode op-amps with stable biasing. VLSI Design 1996: 234-237 - [c17]S. Ramanathan, V. Visvanathan:
A systolic architecture for LMS adaptive filtering with minimal adaptation delay. VLSI Design 1996: 286-289 - 1995
- [c16]V. Visvanathan, S. Ramanathan:
A modular systolic architecture for delayed least mean squares adaptive filtering. VLSI Design 1995: 332-337 - 1994
- [c15]Abhijit Giri, V. Visvanathan, S. K. Nandy, S. K. Ghoshal:
High Speed Digital Filtering on SRAM-Based FPGAs. VLSI Design 1994: 229-232 - [c14]V. K. Anuradha, V. Visvanathan:
A CORDIC Based Programmable DXT Processor Array. VLSI Design 1994: 343-348 - 1993
- [j7]Dinesh Somasekhar, V. Visvanathan:
A 230-MHz half-bit level pipelined multiplier using true single-phase clocking. IEEE Trans. Very Large Scale Integr. Syst. 1(4): 415-422 (1993) - [c13]Pradip Mandal, V. Visvanathan:
Macromodeling of the A.C. characteristics of CMOS Op-amps. ICCAD 1993: 334-340 - [c12]Kalluri Eswar, P. Sadayappan, Chua-Huang Huang, V. Visvanathan:
Supernodal Sparse Cholesky Facotrization on Distributed-Memory Multiprocessors. ICPP (3) 1993: 18-22 - [c11]S. K. Nandy, Ranjani Narayan, V. Visvanathan, P. Sadayappan, Prashant S. Chauhan:
A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor Array. ICPP (3) 1993: 94-97 - [c10]V. Visvanathan, Nibedita Mohanty, S. Ramanathan:
An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response Filters. VLSI Design 1993: 166-171 - [c9]S. Ramanathan, Nibedita Mohanty, V. Visvanathan:
A Methodology for Generating Application Specific Tree Multipliers. VLSI Design 1993: 176-179 - [c8]Debabrata Ghosh, S. K. Nandy, K. Parthasarathy, V. Visvanathan:
NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput Designs. VLSI Design 1993: 341-346 - [c7]Dinesh Somasekhar, V. Visvanathan:
A 230MHz Half Bit Level Pipelined Multiplier Using True Single Phase Clocking. VLSI Design 1993: 347-350 - 1991
- [c6]Kalluri Eswar, P. Sadayappan, V. Visvanathan:
Multifrontal Factorization of Sparse Matrices on Shared-Memory Multiprocessors. ICPP (3) 1991: 159-166
1980 – 1989
- 1989
- [j6]Linda S. Milor, V. Visvanathan:
Detection of catastrophic faults in analog integrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(2): 114-130 (1989) - [j5]P. Sadayappan, V. Visvanathan:
Efficient sparse matrix factorization for circuit simulation on vector supercomputers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(12): 1276-1285 (1989) - [c5]P. Sadayappan, V. Visvanathan:
Efficient Sparse Matrix Factorization for Circuit Simulation on Vector Supercomputers. DAC 1989: 13-18 - [c4]Antony P.-C. Ng, V. Visvanathan:
A Framework for Scheduling Multi-Rate Circuit Simulation. DAC 1989: 19-24 - 1988
- [j4]P. Sadayappan, V. Visvanathan:
Circuit Simulation on Shared-Memory Multiprocessors. IEEE Trans. Computers 37(12): 1634-1642 (1988) - [c3]P. Sadayappan, V. Visvanathan:
Comparative analysis of approaches to hardware acceleration for sparse-matrix factorization. ICCD 1988: 32-35 - [c2]P. Sadayappan, V. Visvanathan:
Parallelization and performance evaluation of circuit simulation on a shared-memory multiprocessor. ICS 1988: 254-265 - 1986
- [c1]V. Visvanathan, Linda S. Milor:
An Efficient Algorithm to Determine the Image of a Parallelepiped Under a Linear Transformation. SCG 1986: 207-215 - 1984
- [j3]V. Visvanathan, Alberto L. Sangiovanni-Vincentelli:
A Computational Approach for the Diagnosability of Dynamical Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3(3): 165-171 (1984) - 1981
- [j2]V. Visvanathan, Alberto L. Sangiovanni-Vincentelli:
Diagnosability of Nonlinear Circuits and Systems - Part I: The dc Case. IEEE Trans. Computers 30(11): 889-898 (1981) - [j1]Richard Saeks, Alberto L. Sangiovanni-Vincentelli, V. Visvanathan:
Diagnosability of Nonlinear Circuits and Systems - Part II: Dynamical Systems. IEEE Trans. Computers 30(11): 899-904 (1981)
Coauthor Index
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