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ORCIDHiroaki Nambu
- > Home > Persons > Hiroaki Nambu
Publications
- 2000
[j8]Takeshi Suzuki, Keiichi Higeta, Yasuhiro Fujimura, Kazumasa Ando, Hiroaki Nambu, Ryo Yamagata, Atsuo Hotta, Kunihiko Yamaguchi:
Synonym hit RAM - a 500-MHz CMOS SRAM macro with 576-bit parallel comparison and parity check functions. IEEE J. Solid State Circuits 35(2): 163-174 (2000)- [j7]Kenichi Ohhata, Fumihiko Arakawa, Takeshi Kusunoki, Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Masahiko Nishiyama, Kunihiko Yamaguchi, Noriyuki Homma, Atsuo Hotta:
Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz. IEEE J. Solid State Circuits 35(4): 564-571 (2000) - [j6]Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Masahiko Nishiyama, Kenichi Ohhata, Fumihiko Arakawa, Takeshi Kusunoki, Kunihiko Yamaguchi, Atsuo Hotta, Noriyuki Homma:
A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM. IEEE J. Solid State Circuits 35(8): 1159-1168 (2000) - 1998
- [j5]Hiroaki Nambu, Kazuo Kanetani, Kaname Yamasaki, Keiichi Higeta, Masami Usami, Yasuhiro Fujimura, Kazumasa Ando, Takeshi Kusunoki, Kunihiko Yamaguchi, Noriyuki Homma:
A 1.8-ns access, 550-MHz, 4.5-Mb CMOS SRAM. IEEE J. Solid State Circuits 33(11): 1650-1658 (1998) - 1996
- [j4]Keiichi Higeta, Masami Usami, Masayuki Ohayashi, Yasuhiro Fujimura, Masahiko Nishiyama, Satoru Isomura, Kunihiko Yamaguchi, Youji Idei, Hiroaki Nambu, Kenichi Ohhata, Nadateru Hanta:
A soft-error-immune 0.9-ns 1.15-Mb ECL-CMOS SRAM with 30-ps 120 k logic gates and on-chip test circuitry. IEEE J. Solid State Circuits 31(10): 1443-1450 (1996) - 1994
- [j3]Nobuo Tamba, Akio Anzai, Kazuhiro Akimoto, Masayuki Ohayashi, Toshiro Hiramoto, Tadanori Kokubu, Sohei Ohmori, Tetsuya Muraya, Atsuyuki Kishimoto, Sousuke Tsuji, Hideki Hayashi, Nadateru Handa, Toshio Igarashi, Hiroaki Nambu, Makoto Yoshida, Tsuyoshi Fujiwara, Kunihiko Watanabe, Akihisa Uchida, Masanori Odaka, Kunihiko Yamaguchi, Takahide Ikeda:
A 1.5-ns 256-kb BiCMOS SRAM with 60-ps 11-K logic gates. IEEE J. Solid State Circuits 29(11): 1344-1352 (1994) - 1992
- [j2]Kunihiko Yamaguchi, Hiroaki Nambu, Kazuo Kanetani, Youji Idei, Noriyuki Homma, Toshiro Hiramoto, Nobuo Tamba, Kunihiko Watanabe, Masanori Odaka, Takahide Ikeda, Kenichi Ohhata, Yoshiaki Sakurai:
A 1.5-ns access time, 78- mu m2 memory-cell size, 64-kb ECL-CMOS SRAM. IEEE J. Solid State Circuits 27(2): 167-174 (1992) - [j1]Hiroaki Nambu, Kazuo Kanetani, Youji Idei, Noriyuki Homma, Kunihiko Yamaguchi, Toshiro Hiramoto, Nobuo Tamba, Masanori Odaka, Kunihiko Watanabe, Takahide Ikeda, Kenichi Ohhata, Yoshiaki Sakurai:
High-speed sensing techniques for ultrahigh-speed SRAMs. IEEE J. Solid State Circuits 27(4): 632-640 (1992)
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