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ORCIDWolfgang Meyer 0002
Person information
- affiliation: Oldenbourg University of Paderborn, Germany
- affiliation: German National Research Center for Computer Science, St. Augustin, Germany
Other persons with the same name
- Wolfgang Meyer — disambiguation page
- Wolfgang Meyer 0001 — University of Osnabrück, Germany
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1990 – 1999
- 1998
[c5]Andrew Seawright, Wolfgang Meyer:
Partitioning and Optimizing Controllers Synthesized from Hierarchical High-Level Descriptions. DAC 1998: 770-775- 1997
- [c4]Wolfgang Meyer, Andrew Seawright, Fumiya Tada:
Design and Synthesis of Array Structured Telecommunication Processing Applications. DAC 1997: 486-491 - 1996
- [c3]Andrew Seawright, Joseph Buck, Ulrich Holtmann, Wolfgang Meyer, Barry M. Pangrle, Rob Verbrugghe:
A system for compiling and debugging structured data processing controllers. EURO-DAC 1996: 86-91 - 1995
- [j3]Wolfgang Meyer, Raul Camposano:
Active timing multilevel fault-simulation with switch-level accuracy. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(10): 1241-1256 (1995) - 1994
- [b1]Wolfgang Meyer:
Hierarchische Mehr-Ebenen-Fehlersimulation mit Modellen der Schalter-Ebene. University of Paderborn, Germany, Oldenbourg 1994, ISBN 978-3-486-23214-1, pp. 1-141 - 1993
- [j2]Heinrich Theodor Vierhaus, Wolfgang Meyer, Uwe Gläser, Raul Camposano:
Fault behavior and testability of asynchronous CMOS circuits. Microprocess. Microprogramming 38(1-5): 223-228 (1993) - [c2]Wolfgang Meyer, Raul Camposano:
Fast Hierarchical Multi-Level Fault Simulation of Sequential Circuits with Switch-Level Accuracy. DAC 1993: 515-519 - [c1]Heinrich Theodor Vierhaus, Wolfgang Meyer, Uwe Gläser:
CMOS Bridges and Resistive Transistor Faults: IDDQ versus Delay Effects. ITC 1993: 83-91 - 1992
- [j1]Uwe Hübner, Wolfgang Meyer, Heinrich Theodor Vierhaus:
CMOS transistor faults and bridging faults: Testability by delay effects and overcurrents. Microprocess. Microprogramming 35(1-5): 377-382 (1992)
Coauthor Index
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