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ORCIDAnirban Sengupta
This is just a disambiguation page, and is not intended to be the bibliography of an actual person. The links to all actual bibliographies of persons of the same or a similar name can be found below. Any publication listed on this page has not been assigned to an actual author yet. If you know the true author of one of the publications listed below, you are welcome to contact us.
Person information
Other persons with the same name
- Anirban Sengupta 0001
![[0000-0002-6239-256X]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0002-6239-256X")
— Jadapur University, Kolkata, India - Anirban Sengupta 0002 — Vanderbilt University Institute of Imaging Science, Nashville, TN, USA
- Anirban Sengupta 0003 — Indian Institute of Technology Indore, Indore, India
- Anirban Sengupta 0004 — Sikkim Manipal Institute of Technology, SMU, Sikkim, India
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2020 – today
- 2021
[j11]Arindam Das, Manoj Kumar Gangwar, Devleena Ghosh, Chittaranjan Mandal, Anirban Sengupta, M. Mubashshir Waris:
Automatic Generation of Route Control Chart From Validated Signal Interlocking Plan. IEEE Trans. Intell. Transp. Syst. 22(10): 6516-6525 (2021)
2010 – 2019
- 2019
- [e1]Anirban Sengupta, Sudeb Dasgupta, Virendra Singh, Rohit Sharma, Santosh Kumar Vishvakarma:
VLSI Design and Test - 23rd International Symposium, VDAT 2019, Indore, India, July 4-6, 2019, Revised Selected Papers. Communications in Computer and Information Science 1066, Springer 2019, ISBN 978-981-32-9766-1 [contents] - 2018
- [j10]Deepak Kachave, Anirban Sengupta, Shubha Neema, Panugothu Sri Harsha:
Effect of NBTI stress on DSP cores used in CE devices: threat model and performance estimation. IET Comput. Digit. Tech. 12(6): 268-278 (2018) - [c13]Anirban Sengupta, Deepak Kachave:
Integrating Compiler Driven Transformation and Simulated Annealing Based Floorplan for Optimized Transient Fault Tolerant DSP Cores. iSES 2018: 17-20 - 2017
- [j9]Anirban Sengupta:
Hardware Security of CE Devices [Hardware Matters]. IEEE Consumer Electron. Mag. 6(1): 130-133 (2017) - [j8]Anirban Sengupta:
Hardware Vulnerabilities and Their Effects on CE Devices: Design for Security Against Trojans [Hardware Matters]. IEEE Consumer Electron. Mag. 6(3): 126-133 (2017) - [c12]Srijita Basu, Anirban Sengupta, Chandan Mazumdar:
A Quantitative Methodology for Cloud Security Risk Assessment. CLOSER 2017: 92-103 - [c11]Anirban Sengupta, Deepak Kachave, Shubha Neema, Panugothu Sri Harsha:
Reliability and Threat Analysis of NBTI Stress on DSP Cores. iNIS 2017: 11-14 - [c10]Anirban Sengupta, Dipanjan Roy:
Mathematical Validation of HWT Based Lossless Image Compression. iNIS 2017: 20-22 - [c9]Vipul Kumar Mishra, Anirban Sengupta:
Comprehensive Operation Chaining Based Schedule Delay Estimation During High Level Synthesis. iNIS 2017: 66-68 - 2016
- [j7]Anirban Sengupta:
Design Flow of a Digital IC: The role of digital IC/SOC design in CE products. IEEE Consumer Electron. Mag. 5(2): 58-62 (2016) - [j6]Anirban Sengupta:
Evolution of the IP Design Process in the Semiconductor/EDA Industry Hardware Matters. IEEE Consumer Electron. Mag. 5(2): 123-126 (2016) - [j5]Anirban Sengupta:
Soft IP Core Design Resiliency Against Terrestrial Transient Faults for CE Products [Hardware Matters]. IEEE Consumer Electron. Mag. 5(4): 129-131 (2016) - [c8]Deepak Kachave, Anirban Sengupta:
Protecting Ownership of Reusable IP Core Generated during High Level Synthesis. iNIS 2016: 80-82 - [c7]Anirban Sengupta, Deepak Kachave:
Generating Multi-cycle and Multiple Transient Fault Resilient Design During Physically Aware High Level Synthesis. ISVLSI 2016: 75-80 - 2014
- [j4]Jaya Bhattacharjee, Anirban Sengupta, Chandan Mazumdar, Mridul Sankar Barik:
A two-phase quantitative methodology for enterprise information security risk analysis. Comput. Syst. Sci. Eng. 29(1) (2014) - [c6]Anirban Sengupta, Vipul Kumar Mishra:
Time Varying vs. Fixed Acceleration Coefficient PSO Driven Exploration during High Level Synthesis: Performance and Quality Assessment. ICIT 2014: 281-286 - [c5]Vipul Kumar Mishra, Anirban Sengupta:
PSDSE: Particle Swarm Driven Design Space Exploration of Architecture and Unrolling Factors for Nested Loops in High Level Synthesis. ISED 2014: 10-14 - [c4]Anirban Sengupta, Vipul Kumar Mishra:
Swarm Intelligence Driven Simultaneous Adaptive Exploration of Datapath and Loop Unrolling Factor during Area-Performance Tradeoff. ISVLSI 2014: 106-111 - 2011
- [j3]Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng:
Multi-objective efficient design space exploration and architectural synthesis of an application specific processor (ASP). Microprocess. Microsystems 35(4): 392-404 (2011) - [j2]Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng:
Rapid design space exploration by hybrid fuzzy search approach for optimal architecture determination of multi objective computing systems. Microelectron. Reliab. 51(2): 502-512 (2011) - [c3]Anirban Sengupta, Reza Sedaghat:
Integrated scheduling, allocation and binding in High Level Synthesis using multi structure genetic algorithm based design space exploration. ISQED 2011: 486-494 - 2010
- [j1]Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng:
A high level synthesis design flow with a novel approach for efficient design space exploration in case of multi-parametric optimization objective. Microelectron. Reliab. 50(3): 424-437 (2010) - [c2]Anirban Sengupta, Reza Sedaghat, Zhipeng Zeng:
Rapid design space exploration for multi parametric optimization of VLSI designs. ISCAS 2010: 3164-3167 - [c1]Zhipeng Zeng, Reza Sedaghat, Anirban Sengupta:
A framework for fast design space exploration using fuzzy search for VLSI computing Architectures. ISCAS 2010: 3176-3179
Coauthor Index
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