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Journal Articles
- 2006
[j3]Michael C. Gaidis
, Eugene J. O'Sullivan, Janusz Jozef Nowak, Yu Lu, Sivananda K. Kanakasabapathy, Philip Louis Trouilloud, Daniel Christopher Worledge, Solomon Assefa, Keith R. Milkove, George P. Wright, William J. Gallagher:
Two-level BEOL processing for rapid iteration in MRAM development. IBM J. Res. Dev. 50(1): 41-54 (2006)- [j2]David William Abraham, Philip Louis Trouilloud, Daniel Christopher Worledge:
Rapid-turnaround characterization methods for MRAM development. IBM J. Res. Dev. 50(1): 55-68 (2006) - [j1]Daniel Christopher Worledge:
Single-domain model for toggle MRAM. IBM J. Res. Dev. 50(1): 69-80 (2006)
Conference and Workshop Papers
- 2024
- [c5]M. G. Gottwald, Guohan Hu, Philip Louis Trouilloud, L. Rehm, C. Safranski, G. Kim, S. L. Brown, J. Bruley, C. P. D'Emic, O. Gunawan, H. Jung, C. Lavoie, J. Lee, J. Liang, M. Robbins, J. Z. Sun, P. Hashemi, Daniel Christopher Worledge:
First Demonstration of High Retention Energy Barriers and 2 ns Switching, Using Magnetic Ordered-Alloy-Based STT MRAM Devices. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c4]Daniel Christopher Worledge:
Write-error-rate of Spin-Transfer-Torque MRAM (Invited). IRPS 2023: 1-4 - 2022
- [c3]Daniel Christopher Worledge:
Spin-Transfer-Torque MRAM: the Next Revolution in Memory. IMW 2022: 1-4 - [c2]C. Safranski, Guohan Hu, J. Z. Sun, P. Hashemi, S. L. Brown, L. Buzi, C. P. D'Emic, E. R. J. Edwards, Eileen A. Galligan, M. G. Gottwald, O. Gunawan, S. Karimeddiny, H. Jung, J. Kim, Kenneth F. Latzko, Philip Louis Trouilloud, S. Zare, Daniel Christopher Worledge:
Reliable Sub-nanosecond MRAM with Double Spin-torque Magnetic Tunnel Junctions. VLSI Technology and Circuits 2022: 288-289 - 2017
- [c1]Guohan Hu, J. J. Nowak, G. Lauer, J. H. Lee, J. Z. Sun, J. Harms, Anthony J. Annunziata, S. Brown, W. Chen, Y. H. Kim, N. Marchack, S. Murthy, Chandrasekharan Kothandaraman, Eugene J. O'Sullivan, J. H. Park, M. Reuter, R. P. Robertazzi, Philip Louis Trouilloud, Y. Zhu, Daniel Christopher Worledge:
Low-current Spin Transfer Torque MRAM. VLSI-DAT 2017: 1-2
Coauthor Index
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