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ORCIDPeter Figuli
Person information
- affiliation: Karlsruhe Institute of Technology, Germany
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2020 – today
- 2022
[c13]Cédric Lichtenau, Alper Buyuktosunoglu, Ramon Bertran, Peter Figuli, Christian Jacobi, Nikolaos Papandreou, Haris Pozidis, Anthony Saporito, Andrew Sica, Elpida Tzortzatos:
AI accelerator on IBM telum processor: industrial product. ISCA 2022: 1012-1028
2010 – 2019
- 2017
- [c12]Peter Figuli, Weiqiao Ding, Shalina Percy Delicia Figuli, Kostas Siozios
, Dimitrios Soudris, Jürgen Becker:
Parameter Sensitivity in Virtual FPGA Architectures. ARC 2017: 141-153 - [c11]Shalina Percy Delicia Figuli, Peter Figuli, Jürgen Becker:
A reconfigurable high-speed spiral FIR filter architecture. TSP 2017: 532-537 - 2016
- [j2]Matthias Birk, Ernst Kretzek, Peter Figuli, Marc Weber, Jürgen Becker, Nicole V. Ruiter:
High-Speed Medical Imaging in 3D Ultrasound Computer Tomography. IEEE Trans. Parallel Distributed Syst. 27(2): 455-467 (2016) - [c10]Shalina Percy Delicia Figuli, Alberto Sonnino, Peter Figuli, Jürgen Becker:
A variable FPGA based generic QAM transmitter with scalable mixed time and frequency domain signal processing. TSP 2016: 453-457 - 2015
- [c9]Kostas Siozios, Peter Figuli, Harry Sidiropoulos, Carsten Tradowsky, Dionysios Diamantopoulos, Konstantinos Maragos, Shalina Percy Delicia, Dimitrios Soudris, Jürgen Becker:
TEAChER: TEach AdvanCEd Reconfigurable Architectures and Tools. ARC 2015: 103-114 - [c8]Peter Figuli, Carsten Tradowsky, Jose Martinez, Harry Sidiropoulos, Kostas Siozios, Holger Stenschke, Dimitrios Soudris, Jürgen Becker:
A Novel Concept for Adaptive Signal Processing on Reconfigurable Hardware. ARC 2015: 311-320 - [c7]Shalina Percy Delicia, George Ford, Peter Figuli, Jürgen Becker:
Parametric design space exploration for optimizing QAM based high-speed communication. ICCC 2015: 1-5 - [c6]Efstathios Sotiriou-Xanthopoulos, Shalina Percy Delicia, Peter Figuli, Kostas Siozios, George Economakos, Jürgen Becker:
A power estimation technique for cycle-accurate higher-abstraction SystemC-based CPU models. SAMOS 2015: 70-77 - 2013
- [j1]Harry Sidiropoulos, Kostas Siozios, Peter Figuli, Dimitrios Soudris, Michael Hübner, Jürgen Becker:
JITPR: A framework for supporting fast application's implementation onto FPGAs. ACM Trans. Reconfigurable Technol. Syst. 6(2): 7:1-7:12 (2013) - [c5]Harry Sidiropoulos, Peter Figuli, Kostas Siozios, Dimitrios Soudris, Jürgen Becker:
A platform-independent runtime methodology for mapping multiple applications onto FPGAs through resource virtualization. FPL 2013: 1-4 - [c4]Peter Figuli, Carsten Tradowsky, Nadine Gaertner, Jürgen Becker:
ViSA: A highly efficient slot architecture enabling multi-objective ASIP cores. ISSoC 2013: 1-8 - 2012
- [c3]Harry Sidiropoulos, Kostas Siozios, Peter Figuli, Dimitrios Soudris, Michael Hübner:
On Supporting Efficient Partial Reconfiguration with Just-In-Time Compilation. IPDPS Workshops 2012: 328-335 - 2011
- [c2]Peter Figuli, Michael Hübner, Romuald Girardey, Falco Bapp, Thomas Bruckschlögl, Florian Thoma, Jörg Henkel, Jürgen Becker:
A heterogeneous SoC architecture with embedded virtual FPGA cores and runtime Core Fusion. AHS 2011: 96-103 - [c1]Michael Hübner, Peter Figuli, Romuald Girardey, Dimitrios Soudris, Kostas Siozios, Jürgen Becker:
A Heterogeneous Multicore System on Chip with Run-Time Reconfigurable Virtual FPGA Architecture. IPDPS Workshops 2011: 143-149
Coauthor Index
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