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ORCIDBrian P. Degnan
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2020 – today
- 2020
[c16]Stewart J. Thomas
, Brian P. Degnan, Cristel Callupe Chavez, Billy Culver:
Backscatter Ex-Nihilo: Single-component, Fully-passive Backscattering for Microcontrollers. RFID 2020: 1-6
2010 – 2019
- 2017
- [c15]Gregory D. Durgin, Brian P. Degnan:
A better channel code than FM0 for next-generation RFID. RFID 2017: 1-5 - [c14]Brian P. Degnan, Gregory D. Durgin, Suigin Maeda:
On the Simon Cipher 4-block key schedule as a hash. RFID 2017: 36-40 - 2016
- [j5]Brian P. Degnan, Bo Marr, Jennifer Hasler:
Assessing Trends in Performance per Watt for Signal Processing Applications. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 58-66 (2016) - [c13]Brian P. Degnan, Jennifer Hasler:
On the temperature dependence of subthreshold currents in MOS electron inversion layers, revisited. ISCAS 2016: 2074-2077 - 2015
- [c12]Brian P. Degnan, Jennifer Hasler:
Low-power, serial interface for power-constrained devices. MWSCAS 2015: 1-4 - [c11]Francesco Amato, Christopher W. Peterson, Brian P. Degnan, Gregory D. Durgin:
A 45 μW bias power, 34 dB gain reflection amplifier exploiting the tunneling effect for RFID applications. IEEE RFID 2015: 137-144 - [c10]Brian P. Degnan, Gregory D. Durgin:
Asynchronous trigger modulation for RFID systems. RFID-TA 2015: 153-158 - 2013
- [j4]Stephen Brink, Stephen Nease, Paul E. Hasler, Shubha Ramakrishnan, Richard B. Wunderlich, Arindam Basu, Brian P. Degnan:
A Learning-Enabled Neuron Array IC Based Upon Transistor Channel Models of Biological Phenomena. IEEE Trans. Biomed. Circuits Syst. 7(1): 71-81 (2013) - [j3]Bo Marr, Brian P. Degnan, Paul E. Hasler, David V. Anderson:
Scaling Energy Per Operation via an Asynchronous Pipeline. IEEE Trans. Very Large Scale Integr. Syst. 21(1): 147-151 (2013) - 2010
- [j2]Bo Marr, Jason George, Brian P. Degnan, David V. Anderson, Paul E. Hasler:
Error Immune Logic for Low-Power Probabilistic Computing. VLSI Design 2010: 460312:1-460312:9 (2010) - [c9]Brian P. Degnan, Brian J. Duffy, Paul E. Hasler:
Crossbar switch matrix for floating-gate programming over large current ranges. ISCAS 2010: 861-864 - [c8]Craig Schlottmann, Brian P. Degnan, David Abramson, Paul E. Hasler:
Reducing offset errors in MITE systems by precise floating gate programming. ISCAS 2010: 1340-1343 - [c7]Scott Koziol, Craig Schlottmann, Arindam Basu, Stephen Brink, Csaba Petre, Brian P. Degnan, Shubha Ramakrishnan, Paul E. Hasler, Aurele Balavoine:
Live demonstration: Hardware and software infrastructure for a family of floating-gate based FPAAs. ISCAS 2010: 2793 - [c6]Scott Koziol, Craig Schlottmann, Arindam Basu, Stephen Brink, Csaba Petre, Brian P. Degnan, Shubha Ramakrishnan, Paul E. Hasler, Aurele Balavoine:
Hardware and software infrastructure for a family of floating-gate based FPAAs. ISCAS 2010: 2794-2797
2000 – 2009
- 2009
- [c5]Brian P. Degnan, Richard B. Wunderlich, Paul E. Hasler:
Passgate Resistance Estimation based on the Compact EKV Model and Effective Mobility. ISCAS 2009: 2765-2768 - [c4]Bo Marr, Brian P. Degnan, Paul E. Hasler, David V. Anderson:
An Asynchronously Embedded Datapath for Performance Acceleration and Energy Efficiency. ISCAS 2009: 3046-3049 - 2007
- [j1]David W. Graham, Ethan Farquhar, Brian P. Degnan, Christal Gordon, Paul E. Hasler:
Indirect Programming of Floating-Gate Transistors. IEEE Trans. Circuits Syst. I Regul. Pap. 54-I(5): 951-963 (2007) - [c3]Richard B. Wunderlich, Brian P. Degnan, Paul E. Hasler:
Capacitively-Biased Floating-Gate CMOS: a New Logic Family. ISCAS 2007: 3728-3731 - 2005
- [c2]David W. Graham, Ethan Farquhar, Brian P. Degnan, Christal Gordon, Paul E. Hasler:
Indirect programming of floating-gate transistors. ISCAS (3) 2005: 2172-2175 - [c1]Brian P. Degnan, Richard B. Wunderlich, Paul E. Hasler:
Programmable floating-gate techniques for CMOS inverters. ISCAS (3) 2005: 2441-2444
Coauthor Index
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