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ORCIDJia Wang 0003
Person information
- affiliation: Illinois Institute of Technology, Department of Electrical and Computer Engineering, Chicago, IL, USA
- affiliation (PhD 2008): Northwestern University, Electrical Engineering and Computer Science, Evanston, IL, USA
Other persons with the same name
- Jia Wang — disambiguation page
- Jia Wang 0001 — AT&T Labs-Research, Florham Park, NJ, USA (and 1 more)
- Jia Wang 0002 — State University of New York at Buffalo, Department of Electrical and Computer Engineering, NY, USA
- Jia Wang 0004
![[0000-0002-1714-3206]](https://dblp.dagstuhl.de/img/orcid-mark.12x12.png "0000-0002-1714-3206")
— Shanghai Jiao Tong University, Department of Electronic Engineering, Institute of Image Communication and Network Engineering, China - Jia Wang 0005 — Worcester Polytechnic Institute, HIVE Lab, MA, USA
- Jia Wang 0006 — University of Greenwich, Old Royal Naval College, London, UK (and 1 more)
- Jia Wang 0007 — City University of Hong Kong, Department of Electric Engineering, Hong Kong
- Jia Wang 0008 — Shenzhen University, College of Computer Science and Software Engineering, China
- Jia Wang 0009 — Xi'an Jiaotong-Liverpool University, Suzhou, China (and 1 more)
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2020 – today
- 2024
[j7]Yiting Liu, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang:
Hierarchical Graph Learning-Based Floorplanning With Dirichlet Boundary Conditions. IEEE Trans. Very Large Scale Integr. Syst. 32(5): 810-822 (2024)- 2023
- [j6]Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang:
GraphPlanner: Floorplanning with Graph Neural Network. ACM Trans. Design Autom. Electr. Syst. 28(2): 21:1-21:24 (2023) - 2022
- [c17]Yiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng, Li Shang:
Floorplanning with graph attention. DAC 2022: 1303-1308 - 2020
- [i1]Shuyu Kong, You Li, Jia Wang, Amin Rezaei, Hai Zhou:
KNN-enhanced Deep Learning Against Noisy Labels. CoRR abs/2012.04224 (2020)
2010 – 2019
- 2013
- [j5]Jie Wu, Jia Wang, Kun Li, Hai Zhou, Qin Lv, Li Shang, Yihe Sun:
Large-Scale Energy Storage System Design and Optimization for Emerging Electric-Drive Vehicles. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(3): 325-338 (2013) - 2010
- [c16]Debasish Das, Jia Wang, Hai Zhou:
iRetILP: an efficient incremental algorithm for min-period retiming under general delay model. ASP-DAC 2010: 61-67 - [c15]Jia Wang, Kun Li, Qin Lv, Hai Zhou, Li Shang:
Hybrid energy storage system integration for vehicles. ISLPED 2010: 369-374
2000 – 2009
- 2009
- [j4]Jia Wang, Debasish Das, Hai Zhou:
Gate Sizing by Lagrangian Relaxation Revisited. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(7): 1071-1084 (2009) - [c14]Jia Wang, Hai Zhou:
Exploring adjacency in floorplanning. ASP-DAC 2009: 367-372 - [c13]Jia Wang, Hai Zhou:
Risk aversion min-period retiming under process variations. ASP-DAC 2009: 480-485 - 2008
- [c12]Jia Wang, Hai Zhou:
An efficient incremental algorithm for min-area retiming. DAC 2008: 528-533 - [c11]Jia Wang, Hai Zhou:
Linear constraint graph for floorplan optimization with soft blocks. ICCAD 2008: 9-15 - 2007
- [j3]Jia Wang, Hai Zhou:
Optimal Jumper Insertion for Antenna Avoidance Considering Antenna Charge Sharing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(8): 1445-1453 (2007) - [j2]Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Zhou:
Unified Incremental Physical-Level and High-Level Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(9): 1576-1588 (2007) - [c10]Jia Wang, Ming-Yang Kao, Hai Zhou:
Address generation for nanowire decoders. ACM Great Lakes Symposium on VLSI 2007: 525-528 - [c9]Jia Wang, Debasish Das, Hai Zhou:
Gate sizing by Lagrangian relaxation revisited. ICCAD 2007: 111-118 - 2006
- [j1]Chuan Lin, Jia Wang, Hai Zhou:
Clustering for Processing Rate Optimization. IEEE Trans. Very Large Scale Integr. Syst. 14(11): 1264-1275 (2006) - [c8]Zhenyu (Peter) Gu, Yonghong Yang, Jia Wang, Robert P. Dick, Li Shang:
TAPHS: thermal-aware unified physical-level and high-level synthesis. ASP-DAC 2006: 879-885 - [c7]Jia Wang, Hai Zhou:
Optimal jumper insertion for antenna avoidance under ratio upper-bound. DAC 2006: 761-766 - [c6]Jia Wang, Hai Zhou, Ping-Chih Wu:
Processing Rate Optimization by Sequential System Floorplanning. ISQED 2006: 340-345 - 2005
- [c5]Jia Wang, Hai Zhou:
Interconnect estimation without packing via ACG floorplans. ASP-DAC 2005: 1152-1155 - [c4]Zhenyu (Peter) Gu, Jia Wang, Robert P. Dick, Hai Zhou:
Incremental exploration of the combined physical and behavioral design space. DAC 2005: 208-213 - [c3]Chuan Lin, Jia Wang, Hai Zhou:
Clustering for processing rate optimization. ICCAD 2005: 189-195 - 2004
- [c2]Jia Wang, Hai Zhou:
Minimal period retiming under process variations. ACM Great Lakes Symposium on VLSI 2004: 131-135 - [c1]Hai Zhou, Jia Wang:
ACG-Adjacent Constraint Graph for General Floorplans. ICCD 2004: 572-575
Coauthor Index
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