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ORCIDIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 26
Volume 26, Number 1, January 2007
- Enrico Macii:
Editorial. 1 - Xin Li, Padmini Gopalakrishnan, Yang Xu, Lawrence T. Pileggi:
Robust Analog/RF Circuit Design With Projection-Based Performance Modeling. 2-15 - Xin Li, Jiayong Le, Padmini Gopalakrishnan, Lawrence T. Pileggi:
Asymptotic Probability Extraction for Nonnormal Performance Distributions. 16-37 - Michael B. Healy, Mario Vittes, Mongkol Ekpanyapong, Chinnakrishnan S. Ballapuram, Sung Kyu Lim
, Hsien-Hsin S. Lee, Gabriel H. Loh:
Multiobjective Microarchitectural Floorplanning for 2-D and 3-D ICs. 38-52 - Akhilesh Kumar, Mohab Anis:
Dual-Threshold CAD Framework for Subthreshold Leakage Power Aware FPGAs. 53-66 - Ashish Srivastava, T. Kachru, Dennis Sylvester:
Low-Power-Design Space Exploration Considering Process Variation Using Robust Optimization. 67-79 - Shinji Odanaka:
A High-Resolution Method for Quantum Confinement Transport Simulations in MOSFETs. 80-85 - Yonghong Yang, Zhenyu (Peter) Gu, Changyun Zhu, Robert P. Dick, Li Shang:
ISAC: Integrated Space-and-Time-Adaptive Chip-Package Thermal Analysis. 86-99 - Zai-Fa Zhou, Qing-An Huang, Wei-Hua Li, Wei Lu:
A Novel 3-D Dynamic Cellular Automata Model for Photoresist-Etching Process Simulation. 100-114 - Charles C. Chiang, Andrew B. Kahng, Subarna Sinha, Xu Xu, Alexander Zelikovsky:
Fast and Efficient Bright-Field AAPSM Conflict Detection and Correction. 115-126 - Devang Jariwala, John Lillis:
RBI: Simultaneous Placement and Routing Optimization Technique. 127-141 - Taewhan Kim, Jungeun Kim:
Integration of Code Scheduling, Memory Allocation, and Array Binding for Memory-Access Optimization. 142-151 - Kai-Hui Chang, Valeria Bertacco, Igor L. Markov:
Simulation-Based Bug Trace Minimization With BMC-Based Refinement. 152-165 - Wendemagegnehu T. Beyene:
Application of Artificial Neural Networks to Statistical Analysis and Nonlinear Modeling of High-Speed Interconnect Systems. 166-176 - Kyosun Kim, Kaijie Wu, Ramesh Karri:
The Robust QCA Adder Designs Using Composable QCA Building Blocks. 176-183 - Dipanjan Sengupta, Resve A. Saleh:
Generalized Power-Delay Metrics in Deep Submicron CMOS Designs. 183-189 - B. K. S. V. L. Varaprasad, Lalit M. Patnaik, Hirisave S. Jamadagni, V. K. Agrawal:
A New ATPG Technique (ExpoTan) for Testing Analog Circuits. 189-196
Volume 26, Number 2, February 2007
- Kia Bazargan, André DeHon:
Guest Editorial. 201-202 - Ian Kuon, Jonathan Rose:
Measuring the Gap Between FPGAs and ASICs. 203-215 - Mingjie Lin, Abbas El Gamal, Yi-Chang Lu, S. Simon Wong:
Performance Benefits of Monolithically Stacked 3-D FPGA. 216-229 - Jason Cong, Kirill Minkovich:
Optimality Study of Logic Synthesis for LUT-Based FPGAs. 230-239 - Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton:
Improvements to Technology Mapping for LUT-Based FPGAs. 240-253 - Welson Sun, Michael J. Wirthlin, Stephen Neuendorffer:
FPGA Pipeline Synthesis Design Exploration Using Module Selection and Resource Sharing. 254-265 - Peter Yiannacouras, J. Gregory Steffan, Jonathan Rose:
Exploration and Customization of FPGA-Based Soft Processors. 266-277 - Russell Tessier, Vaughn Betz, David Neto, Aaron Egier, Thiagaraja Gopalsamy:
Power-Efficient RAM Mapping Algorithms for FPGA Embedded Memory Blocks. 278-290 - Mark Holland, Scott Hauck:
Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC. 291-295 - Tim Tuan, Arifur Rahman, Satyaki Das, Steven Trimberger, Sean Kao:
A 90-nm Low-Power FPGA for Battery-Powered Applications. 296-300 - Andrew B. Kahng, Ion I. Mandoiu, Xu Xu, Alexander Zelikovsky:
Enhanced Design Flow and Optimizations for Multiproject Wafers. 301-311 - Ismail Kadayif, Partho Nath, Mahmut T. Kandemir, Anand Sivasubramaniam:
Reducing Data TLB Power via Compiler-Directed Address Generation. 312-324 - Baohua Wang, Pinaki Mazumder:
Accelerated Chip-Level Thermal Analysis Using Multilayer Green's Function. 325-344 - Yih-Lang Li, Jin-Yih Li, Wen-Bin Chen:
An Efficient Tile-Based ECO Router Using Routing Graph Reduction and Enhanced Global Routing Flow. 345-358 - Xiaoyong Chen, Douglas L. Maskell, Yang Sun:
Fast Identification of Custom Instructions for Extensible Processors. 359-368 - Dongkun Shin, Jihong Kim:
Optimizing Intratask Voltage Scheduling Using Profile and Data-Flow Information. 369-385 - Kedarnath J. Balakrishnan, Nur A. Touba:
Relationship Between Entropy and Test Data Compression. 386-395 - Jinkyu Lee, Nur A. Touba:
LFSR-Reseeding Scheme Achieving Low-Power Dissipation During Test. 396-401
Volume 26, Number 3, March 2007
- Georges G. E. Gielen, Donatella Sciuto:
Guest Editorial [intro. to the special issue on the 2006 IEEE/ACM Design, Automation and Test in Europe Conference]. 405-407 - Sudeep Pasricha, Nikil D. Dutt:
A Framework for Cosynthesis of Memory and Communication Architectures for MPSoC. 408-420 - Federico Angiolini, Paolo Meloni, Salvatore Carta, Luigi Raffo, Luca Benini:
A Layout-Aware Analysis of Networks-on-Chip and Traditional Interconnects for MPSoCs. 421-434 - Partha Biswas, Nikil D. Dutt, Laura Pozzi, Paolo Ienne:
Introduction of Architecturally Visible Storage in Instruction Set Extensions. 435-446 - Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou:
Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment. 447-455 - Cristian Soviani, Olivier Tardieu, Stephen A. Edwards:
Optimizing Sequential Cycles Through Shannon Decomposition and Retiming. 456-467 - Rajeev R. Rao, Kaviraj Chopra, David T. Blaauw, Dennis Sylvester:
Computing the Soft Error Rate of a Combinational Logic Circuit Using Parameterized Descriptors. 468-479 - Ying Wei, Alex Doboli, Hua Tang:
Systematic Methodology for Designing Reconfigurable DeltaSigma Modulator Topologies for Multimode Communication Systems. 480-496 - Enrico Giunchiglia, Massimo Narizzano, Armando Tacchella:
Quantifier Structure in Search-Based Procedures for QBFs. 497-507 - Li Shang, Robert P. Dick, Niraj K. Jha:
SLOPES: Hardware-Software Cosynthesis of Low-Power Real-Time Distributed Embedded Systems With Dynamically Reconfigurable FPGAs. 508-526 - Chao-Yang Yeh, Malgorzata Marek-Sadowska:
Timing-Aware Power-Noise Reduction in Placement. 527-541 - Anish Muttreja, Anand Raghunathan, Srivaths Ravi, Niraj K. Jha:
Automated Energy/Performance Macromodeling of Embedded Software. 542-552 - Mehdi Baradaran Tahoori, Subhasish Mitra:
Application-Dependent Delay Testing of FPGAs. 553-563 - Wu-An Kuo, Yi-Ling Chiang, TingTing Hwang, Allen C.-H. Wu:
Performance-Driven Crosstalk Elimination at Postcompiler Level-The Case of Low-Crosstalk Op-Code Assignment. 564-573 - Farid N. Najm, Noel Menezes, Imad A. Ferzli:
A Yield Model for Integrated Circuits and its Application to Statistical Timing Analysis. 574-591 - Curtis A. Nelson, Chris J. Myers, Tomohiro Yoneda:
Efficient Verification of Hazard-Freedom in Gate-Level Timed Asynchronous Circuits. 592-605 - B. P. Harish, Navakanta Bhat, Mahesh B. Patil:
On a Generalized Framework for Modeling the Effects of Process Variations on Circuit Delay Performance Using Response Surface Methodology. 606-614
Volume 26, Number 4, April 2007
- Jiang Hu, Patrick H. Madden:
Guest Editorial. 617-618 - Jinjun Xiong, Vladimir Zolotov, Lei He:
Robust Extraction of Spatial Correlation. 619-631 - Jarrod A. Roy, Igor L. Markov:
Seeing the Forest and the Trees: Steiner Wirelength Optimization in Placement. 632-644 - Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Shan Zeng, Jinian Bian, Wenjian Yu, Hannah Honghua Yang, Vijay Pitchumani, Chung-Kuan Cheng:
Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. 645-658 - Shinichi Koda, Chikaaki Kodama, Kunihiro Fujiyoshi:
Linear Programming-Based Cell Placement With Symmetry Constraints for Analog IC Layout. 659-668 - Jianhua Li, Laleh Behjat, Andrew A. Kennings:
Net Cluster: A Net-Reduction-Based Clustering Preprocessing Algorithm for Partitioning and Placement. 669-679 - Jin Shi, Yici Cai, Sheldon X.-D. Tan, Jeffrey Fan, Xianlong Hong:
Pattern-Based Iterative Method for Extreme Large Power/Ground Analysis. 680-692 - Chen-Wei Liu, Yao-Wen Chang:
Power/Ground Network and Floorplan Cosynthesis for Fast Design Convergence. 693-704 - Yih-Lang Li, Hsin-Yu Chen, Chih-Ta Lin:
NEMO: A New Implicit-Connection-Graph-Based Gridless Router With Multilayer Planes and Pseudo Tile Propagation. 705-718 - Bor-Yiing Su, Yao-Wen Chang, Jiang Hu:
An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles. 719-733 - Jun Chen, Lei He:
Efficient In-Package Decoupling Capacitor Optimization for I/O Power Integrity. 734-738 - Jinjun Xiong, Lei He:
Probabilistic Transitive-Closure Ordering and Its Application on Variational Buffer Insertion. 739-742 - Bipul Chandra Paul, Kunhyuk Kang, Haldun Kufluoglu, Muhammad Ashraful Alam, Kaushik Roy:
Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits. 743-751 - Fei Li, Yan Lin, Lei He:
Field Programmability of Supply Voltages for FPGA Power Reduction. 752-764 - Hiren D. Patel, Sandeep K. Shukla, Reinaldo A. Bergamaschi:
Heterogeneous Behavioral Hierarchy Extensions for SystemC. 765-780 - Benny Thörnberg, Martin Palkovic, Qubo Hu, Leif Olsson, Per Gunnar Kjeldsberg, Mattias O'Nils, Francky Catthoor:
Bit-Width Constrained Memory Hierarchy Optimization for Real-Time Video Systems. 781-800 - B. Lasbouygues, Robin Wilson, Nadine Azémard, Philippe Maurine:
Temperature- and Voltage-Aware Timing Analysis. 801-815
Volume 26, Number 5, May 2007
- Chen He, Margarida F. Jacome:
Defect-Aware High-Level Synthesis Targeted at Reconfigurable Nanofabrics. 817-833 - Martin Saint-Laurent:
A Model for Interlevel Coupling Noise in Multilevel Interconnect Structures. 834-844 - Lei He, Andrew B. Kahng, King Ho Tam, Jinjun Xiong:
Simultaneous Buffer Insertion and Wire Sizing Considering Systematic CMP Variation and Random Leff Variation. 845-857 - Chen Li, Min Xie, Cheng-Kok Koh, Jason Cong, Patrick H. Madden:
Routability-Driven Placement and White Space Allocation. 858-871 - Zhuo Li, Nancy Ying Zhou, Weiping Shi:
Wire Sizing for Non-Tree Topology. 872-880 - Zhengyong Zhu, He Peng, Chung-Kuan Cheng, Khosro Rouz, Manjit Borah, Ernest S. Kuh:
Two-Stage Newton-Raphson Method for Transistor-Level Simulation. 881-895 - Nisar Ahmed, Mohammad Tehranipoor, C. P. Ravikumar, Kenneth M. Butler:
Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers. 896-906 - Ahmad A. Al-Yamani, Narendra Devta-Prasanna, Erik Chmelar, M. Grinchuk, Arun Gunda:
Scan Test Cost and Power Reduction Through Systematic Scan Reconfiguration. 907-918 - Jin-Fu Li:
Testing Ternary Content Addressable Memories With Comparison Faults Using March-Like Tests. 919-931 - Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng:
Multiple-Fault Diagnosis Based On Adaptive Diagnostic Test Pattern Generation. 932-942 - Mohammad Tehranipoor, Reza M. Rad:
Built-In Self-Test and Recovery Procedures for Molecular Electronics-Based Nanofabrics. 943-958 - Shuo Zhou, Bo Yao, Hongyu Chen, Yi Zhu, Michael D. Hutton, Truman Collins, Sridhar Srinivasan, Nan-Chi Chou, Peter Suaris, Chung-Kuan Cheng:
Efficient Timing Analysis With Known False Paths Using Biclique Covering. 959-969 - Saihua Lin, Huazhong Yang, Rong Luo:
A Novel gamma d/n, RLCG Transmission Line Model Considering Complex RC(L) Loads. 970-977 - Srinivasa R. Sridhara, Naresh R. Shanbhag:
Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes. 977-982 - Mahilchi Milir Vaseekar Kumar, Spyros Tragoudas:
High-Quality Transition Fault ATPG for Small Delay Defects. 983-989
Volume 26, Number 6, May 2007
- Danil Sokolov, Alexandre V. Bystrov, Alexandre Yakovlev:
Direct Mapping of Low-Latency Asynchronous Controllers From STGs. 993-1009 - Gang Wang, Wenrui Gong, Brian DeRenzi, Ryan Kastner:
Ant Colony Optimizations for Resource- and Timing-Constrained Operation Scheduling. 1010-1029 - Youngjin Cho, Naehyuck Chang:
Energy-Aware Clock-Frequency Assignment in Microprocessors and Memory Devices for Dynamic Voltage Scaling. 1030-1040 - Tai-Chen Chen, Yao-Wen Chang:
Multilevel Full-Chip Gridless Routing With Applications to Optical-Proximity Correction. 1041-1053 - Ting Mei, Jaijeet S. Roychowdhury:
Small-Signal Analysis of Oscillators Using Generalized Multitime Partial Differential Equations. 1054-1069 - Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos:
Multilevel Huffman Coding: An Efficient Test-Data Compression Method for IP Cores. 1070-1083 - Wei Pei, Wen-Ben Jone, Yiming Hu:
Fault Modeling and Detection for Drowsy SRAM Caches. 1084-1100 - Jen-Chieh Yeh, Kuo-Liang Cheng, Yung-Fa Chou, Cheng-Wen Wu:
Flash Memory Testing and Built-In Self-Diagnosis With March-Like Test Algorithms. 1101-1113 - Emre Salman, Ali Dasdan, Feroze Taraporevala, Kayhan Küçükçakar, Eby G. Friedman:
Exploiting Setup-Hold-Time Interdependence in Static Timing Analysis. 1114-1125 - Ilya Wagner, Valeria Bertacco, Todd M. Austin:
Microprocessor Verification via Feedback-Adjusted Markov Models. 1126-1138 - Changzhong Chen, Emad Gad, Natalie Nakhla, Ramachandra Achar:
Analysis of Frequency-Dependent Interconnects Using Integrated Congruence Transform. 1139-1149 - Ming-e Jing, Yue Hao, Dian Zhou, Xuan Zeng:
A Novel Optimization Method for Parametric Yield: Uniform Design Mapping Distance Algorithm. 1149-1155 - Yi-Yu Liu, TingTing Hwang:
Crosstalk-Aware Domino-Logic Synthesis. 1155-1161 - Jiong Luo, Niraj K. Jha:
Power-Efficient Scheduling for Heterogeneous Distributed Real-Time Embedded Systems. 1161-1170 - Irith Pomeranz:
Invariant States and Redundant Logic in Synchronous Sequential Circuits. 1171-1175
Volume 26, Number 7, July 2007
- Tomohiro Yoneda, Chris J. Myers:
Synthesis of Timed Circuits Based on Decomposition. 1177-1195 - Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown:
FPGA PLB Architecture Evaluation and Area Optimization Techniques Using Boolean Satisfiability. 1196-1210 - Lerong Cheng, Fei Li, Yan Lin, Phoebe Wong, Lei He:
Device and Architecture Cooptimization for FPGA Power Reduction. 1211-1221 - Chuan Lin, Hai Zhou:
Tradeoff Between Latch and Flop for Min-Period Sequential Circuit Designs With Crosstalk. 1222-1232 - Rui Zhang, Pallav Gupta, Niraj K. Jha:
Majority and Minority Network Synthesis With Application to QCA-, SET-, and TPL-Based Nanotechnologies. 1233-1245 - Vishal Khandelwal, Ankur Srivastava:
Leakage Control Through Fine-Grained Placement and Sizing of Sleep Transistors. 1246-1255 - Huaizhi Wu, Martin D. F. Wong, I-Min Liu, Yusu Wang:
Placement-Proximity-Based Voltage Island Grouping Under Performance Requirement. 1256-1269 - Lili Zhou, Cherry Wakayama, Chuanjin Richard Shi:
CASCADE: A Standard Supercell Design Methodology With Congestion-Driven Placement for Three-Dimensional Interconnect-Heavy Very Large-Scale Integrated Circuits. 1270-1282 - Srinivasan Murali, Luca Benini, Giovanni De Micheli:
An Application-Specific Design Methodology for On-Chip Crossbar Generation. 1283-1296 - Rutuparna Tamhankar, Srinivasan Murali, Stergios Stergiou, Antonio Pullini, Federico Angiolini, Luca Benini, Giovanni De Micheli:
Timing-Error-Tolerant Network-on-Chip Design Methodology. 1297-1310 - Irith Pomeranz, Sudhakar M. Reddy:
Generation of Broadside Transition-Fault Test Sets That Detect Four-Way Bridging Faults. 1311-1319 - Namrata Shekhar, Sudhakar Kalla, Florian Enescu:
Equivalence Verification of Polynomial Datapaths Using Ideal Membership Testing. 1320-1330 - Shibaji Banerjee, Dipanwita Roy Chowdhury, Bhargab B. Bhattacharya:
An Efficient Scan Tree Design for Compact Test Pattern Set. 1331-1339 - Loganathan Lingappan, Niraj K. Jha:
Efficient Design for Testability Solution Based on Unsatisfiability for Register-Transfer Level Circuits. 1339-1345 - Chin Ngai Sze, Charles J. Alpert, Jiang Hu, Weiping Shi:
Path-Based Buffer Insertion. 1346-1355
Volume 26, Number 8, August 2007
- Alberto L. Sangiovanni-Vincentelli:
Remembering Richard [Obituary, Richard A.Newton]. 1357-1366 - Yongseok Choi, Naehyuck Chang, Taewhan Kim:
DC-DC Converter-Aware Power Management for Low-Power Embedded Systems. 1367-1381 - Pu Liu, Sheldon X.-D. Tan, Bruce McGaughy, Lifeng Wu, Lei He:
TermMerg: An Efficient Terminal-Reduction Method for Interconnect Circuits. 1382-1392 - Bernard N. Sheehan:
Realizable Reduction of RC Networks. 1393-1407 - Michael Spevak, Tibor Grasser:
Discretization of Macroscopic Transport Equations on Non-Cartesian Coordinate Systems. 1408-1416