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Haile Yu
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Journal Articles
- 2012
- [j1]Haile Yu, Philip Heng Wai Leong, Qiang Xu:
An FPGA Chip Identification Generator Using Configurable Ring Oscillators. IEEE Trans. Very Large Scale Integr. Syst. 20(12): 2198-2207 (2012)
Conference and Workshop Papers
- 2012
- [c11]Yubin Zhang, Haile Yu, Qiang Xu:
CODA: A concurrent online delay measurement architecture for critical paths. ASP-DAC 2012: 169-174 - [c10]Jie Zhang, Haile Yu, Qiang Xu:
HTOutlier: Hardware Trojan detection with side-channel signature outlier identification. HOST 2012: 55-58 - 2011
- [c9]Haile Yu, Qiang Xu, Philip Heng Wai Leong:
On timing yield improvement for FPGA designs using architectural symmetry (abstract only). FPGA 2011: 278 - [c8]Haile Yu, Qiang Xu, Philip Heng Wai Leong:
On Timing Yield Improvement for FPGA Designs Using Architectural Symmetry. FPL 2011: 539-544 - 2010
- [c7]Haile Yu, Qiang Xu, Philip Heng Wai Leong:
Fine-grained characterization of process variation in FPGAs. FPT 2010: 138-145 - [c6]Haile Yu, Philip Heng Wai Leong, Qiang Xu:
An FPGA chip identification generator using configurable ring oscillator. FPT 2010: 312-315 - 2009
- [c5]Haile Yu, Philip Heng Wai Leong, Heiko Hinkelmann, Leandro Möller, Manfred Glesner, Peter Zipf:
Towards a unique FPGA-based identification circuit using process variations. FPL 2009: 397-402 - [c4]Eddie Hung, Steven J. E. Wilton, Haile Yu, Thomas C. P. Chau, Philip Heng Wai Leong:
A detailed delay path model for FPGAs. FPT 2009: 96-103 - 2008
- [c3]Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong:
FPGA interconnect design using logical effort. FPGA 2008: 257 - [c2]Haile Yu, Yuk Hei Chan, Philip Heng Wai Leong:
FPGA interconnect design using logical effort. FPL 2008: 447-450 - [c1]Haile Yu:
FPGA interconnect sizing using extended logical effort model. FPL 2008: 695-696
Coauthor Index
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