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2020 – today
- 2023
[c25]Guillaume Soudais, Tarik Graba, Yves Mathieu, Sébastien Bigo:
Jitter Compensation Mechanism for Dynamic Deterministic Networks. OFC 2023: 1-3- 2021
- [j8]Ville Yli-Mäyry
, Rei Ueno, Noriyuki Miura, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Naofumi Homma:
Diffusional Side-Channel Leakage From Unrolled Lightweight Block Ciphers: A Case Study of Power Analysis on PRINCE. IEEE Trans. Inf. Forensics Secur. 16: 1351-1364 (2021) - [c24]Sofiane Takarabt, Sylvain Guilley, Youssef Souissi, Khaled Karray, Laurent Sauvage, Yves Mathieu:
Formal Evaluation and Construction of Glitch-resistant Masked Functions. HOST 2021: 304-313 - 2020
- [j7]Rei Ueno, Naofumi Homma, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger:
High Throughput/Gate AES Hardware Architectures Based on Datapath Compression. IEEE Trans. Computers 69(4): 534-548 (2020)
2010 – 2019
- 2019
- [c23]Sofiane Takarabt, Alexander Schaub, Adrien Facon, Sylvain Guilley, Laurent Sauvage, Youssef Souissi, Yves Mathieu:
Cache-Timing Attacks Still Threaten IoT Devices. C2SI 2019: 13-30 - 2018
- [c22]Jean-Luc Danger, Risa Yashiro, Tarik Graba, Yves Mathieu, Abdelmalek Si-Merabet, Kazuo Sakiyama, Noriyuki Miura, Makoto Nagata:
Analysis of Mixed PUF-TRNG Circuit Based on SR-Latches in FD-SOI Technology. DSD 2018: 508-515 - [c21]Sofiane Takarabt, Kais Chibani, Adrien Facon, Sylvain Guilley, Yves Mathieu, Laurent Sauvage, Youssef Souissi:
Pre-silicon Embedded System Evaluation as New EDA Tool for Security Verification. IVSW 2018: 74-79 - 2017
- [j6]Xuan Thuy Ngo, Jean-Luc Danger, Sylvain Guilley, Tarik Graba, Yves Mathieu, Zakaria Najm, Shivam Bhasin:
Cryptographically Secure Shield for Security IPs Protection. IEEE Trans. Computers 66(2): 354-360 (2017) - 2016
- [i1]Sumanta Chaudhuri, Tarik Graba, Yves Mathieu:
Multi-Valued Routing Tracks for FPGAs in 28nm FDSOI Technology. CoRR abs/1609.08681 (2016) - 2015
- [c20]Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger:
Countering early propagation and routing imbalance of DPL designs in a tree-based FPGA. ICICDT 2015: 1-4 - 2014
- [c19]Shivam Bhasin, Jean-Luc Danger, Tarik Graba, Yves Mathieu, Daisuke Fujimoto, Makoto Nagata:
Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology. ES4CPS@DATE 2014: 13 - [c18]Emna Amouri, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger, Habib Mehrez:
Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security. FPL 2014: 1-4 - [c17]Jean-Michel Cioranesco, Jean-Luc Danger, Tarik Graba, Sylvain Guilley, Yves Mathieu, David Naccache, Xuan Thuy Ngo:
Cryptographically secure shields. HOST 2014: 25-31 - 2013
- [c16]Zouha Cherif, Jean-Luc Danger, Florent Lozach, Yves Mathieu, Lilian Bossuet:
Evaluation of delay PUFs on CMOS 65 nm technology: ASIC vs FPGA. HASP@ISCA 2013: 4 - [c15]Molka Ben-Romdhane, Tarik Graba, Jean-Luc Danger, Yves Mathieu:
Design methodology of an ASIC TRNG based on an open-loop delay chain. NEWCAS 2013: 1-4 - [p1]Jean Le Feuvre, Yves Mathieu:
Graphics Composition for Multiview Displays. Emerging Technologies for 3D Video 2013: 450-467 - 2012
- [j5]Laurent Sauvage, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu:
Blind Cartography for Side Channel Attacks: Cross-Correlation Cartography. Int. J. Reconfigurable Comput. 2012: 360242:1-360242:9 (2012) - [j4]Stéphane Mancini, Zahir Larabi, Yves Mathieu, Tomasz Toczek, Lionel Pierrefeu:
Exploration of 3D grid caching strategies for ray-shooting. J. Real Time Image Process. 7(1): 3-19 (2012) - [c14]Mariem Slimani, Philippe Matherat, Yves Mathieu:
A dual threshold voltage technique for glitch minimization. ICECS 2012: 444-447 - 2010
- [j3]Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu:
Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics. Int. J. Reconfigurable Comput. 2010: 375245:1-375245:12 (2010) - [c13]Asmaa Al-Naqi, Ahmet T. Erdogan, Tughrul Arslan, Yves Mathieu:
Balancing exploration and exploitation in an adaptive three-dimensional cellular genetic algorithm via a probabilistic selection operator. AHS 2010: 258-264 - [c12]Stéphane Mancini, Lionel Pierrefeu, Zahir Larabi, Yves Mathieu:
Calibrating a predictive cache emulator for SoC design. AHS 2010: 273-280 - [c11]Laurent Sauvage, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu:
Cross-Correlation Cartography. ReConFig 2010: 268-273
2000 – 2009
- 2009
- [j2]Laurent Sauvage, Sylvain Guilley, Yves Mathieu:
Electromagnetic Radiations of FPGAs: High Spatial Resolution Cartography and Attack on a Cryptographic Module. ACM Trans. Reconfigurable Technol. Syst. 2(1): 4:1-4:24 (2009) - [c10]Laurent Sauvage, Sylvain Guilley, Jean-Luc Danger, Yves Mathieu, Maxime Nassar:
Successful attack on an FPGA-based WDDL DES cryptoprocessor without place and route constraints. DATE 2009: 640-645 - [c9]Zahir Larabi, Yves Mathieu, Stéphane Mancini:
High Efficiency Reconfigurable Cache for Image Processing. ERSA 2009: 226-232 - [c8]Shivam Bhasin, Jean-Luc Danger, Florent Flament, Tarik Graba, Sylvain Guilley, Yves Mathieu, Maxime Nassar, Laurent Sauvage, Nidhal Selmane:
Combined SCA and DFA Countermeasures Integrable in a FPGA Design Flow. ReConFig 2009: 213-218 - [c7]Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu:
DPL on Stratix II FPGA: What to Expect?. ReConFig 2009: 243-248 - [c6]Zahir Larabi, Yves Mathieu, Stéphane Mancini:
Efficient Data Access Management for FPGA-Based Image Processing SoCs. IEEE International Workshop on Rapid System Prototyping 2009: 159-165 - 2008
- [c5]Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Tarik Graba, Yves Mathieu:
Evaluation of Power-Constant Dual-Rail Logic as a Protection of Cryptographic Applications in FPGAs. SSIRI 2008: 16-23 - 2007
- [j1]Sylvain Guilley, Florent Flament, Philippe Hoogvorst, Renaud Pacalet, Yves Mathieu:
Secured CAD Back-End Flow for Power-Analysis-Resistant Cryptoprocessors. IEEE Des. Test Comput. 24(6): 546-555 (2007) - 2005
- [c4]Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet:
The "Backend Duplication" Method. CHES 2005: 383-397 - 2004
- [c3]Sylvain Guilley, Philippe Hoogvorst, Yves Mathieu, Renaud Pacalet, Jean Provost:
CMOS Structures Suitable for Secured Hardware. DATE 2004: 1414-1415 - 2003
- [c2]Christophe Cunat, Jean Gobert, Yves Mathieu:
A coprocessor for real-time MPEG4 facial animation on mobiles. ESTIMedia 2003: 102-108
1980 – 1989
- 1988
- [c1]Paul Winser, Thierry Bonnet, Dominique Dumont, Yves Mathieu:
Architectures for Mass Market 3D Displays. Eurographics 1988
Coauthor Index
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