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Joe Swenton
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Journal Articles
- 2024
- [j2]Zhan Gao, Min-Chun Hu, Rogier Baert, Bilal Chehab, Joe Swenton, Santosh Malagi, Jos Huisken, Kees Goossens, Erik Jan Marinissen:
Cell-Aware Test on Various Circuits in an Advanced 3-nm Technology. IEEE Des. Test 41(2): 56-64 (2024) - 2021
- [j1]Zhan Gao, Min-Chun Hu, Santosh Malagi, Joe Swenton, Jos Huisken, Kees Goossens, Erik Jan Marinissen:
Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality. J. Electron. Test. 37(2): 161-189 (2021)
Conference and Workshop Papers
- 2021
- [c11]Francesco Lorenzelli, Zhan Gao, Joe Swenton, Santosh Malagi, Erik Jan Marinissen:
Speeding up Cell-Aware Library Characterization by Preceding Simulation with Structural Analysis. ETS 2021: 1-6 - 2020
- [c10]Min-Chun Hu, Zhan Gao, Santosh Malagi, Joe Swenton, Jos Huisken, Kees Goossens, Cheng-Wen Wu, Erik Jan Marinissen:
Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching All Detectable Weakest Faults. ETS 2020: 1-6 - 2019
- [c9]Zhan Gao, Santosh Malagi, Min-Chun Hu, Joe Swenton, Rogier Baert, Jos Huisken, Bilal Chehab, Kees Goossens, Erik Jan Marinissen:
Application of Cell-Aware Test on an Advanced 3nm CMOS Technology Library. ITC 2019: 1-6 - [c8]Zhan Gao, Min-Chun Hu, Joe Swenton, Santosh Malagi, Jos Huisken, Kees Goossens, Erik Jan Marinissen:
Optimization of Cell-Aware ATPG Results by Manipulating Library Cells' Defect Detection Matrices. ITC-Asia 2019: 91-96 - [c7]Zhan Gao, Santosh Malagi, Erik Jan Marinissen, Joe Swenton, Jos Huisken, Kees Goossens:
Defect-Location Identification for Cell-Aware Test. LATS 2019: 1-6 - 2018
- [c6]Sameer Chillarige, Atul Chhabra, Anil Malik, Bharath Nandakumar, Joe Swenton, Krishna Chakravadhanula:
Improving Diagnosis Resolution and Performance at High Compression Ratios. ITC 2018: 1-8 - 2017
- [c5]Sameer Chillarige, Anil Malik, Sharjinder Singh, Joe Swenton, Krishna Chakravadhanula:
High throughput multiple device diagnosis system. ITC 2017: 1-10 - 2015
- [c4]Sameer Chillarige, S. Virdi, Anil Malik, Krishna Chakravadhanula, Vivek Chickermane, Joe Swenton, G. Vandling:
A Novel Failure Diagnosis Approach for Low Pin Count and Low Power Compression Architectures. NATW 2015: 43-48 - 2000
- [c3]Robert Butler, Brion L. Keller, Sarala Paliwal, Richard Schoonover, Joseph Swenton:
Design and implementation of a parallel automatic test pattern generation algorithm with low test vector count. ITC 2000: 530-537 - 1999
- [c2]Xinghao Chen, Thomas J. Snethen, Joe Swenton, Ron Walther:
A Simplified Method for Testing the IBM Pipeline Partial-Scan Microprocessor. Asian Test Symposium 1999: 321-326 - 1998
- [c1]Brion L. Keller, Kevin McCauley, Joseph Swenton, James Youngs:
ATPG in practical and non-traditional applications. ITC 1998: 632-640
Coauthor Index
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