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Conference and Workshop Papers
- 2020
[c8]Tsung-Fu Hsieh, Jin-Fu Li, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
Refresh Power Reduction of DRAMs in DNN Systems Using Hybrid Voting and ECC Method. ITC-Asia 2020: 41-46- 2018
- [c7]Kuan-Te Wu, Jin-Fu Li, Chih-Yen Lo, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou:
A channel-sharable built-in self-test scheme for multi-channel DRAMs. ASP-DAC 2018: 245-250 - 2017
- [c6]Tah-Kang Joseph Ting, Gyh-Bin Wang, Ming-Hung Wang, Chun-Peng Wu, Chun-Kai Wang, Chun-Wei Lo, Li-Chin Tien, Der-Min Yuan, Yung-Ching Hsieh, Jenn-Shiang Lai, Wen-Pin Hsu, Chien-Chih Huang, Chi-Kang Chen, Yung-Fa Chou, Ding-Ming Kwai, Zhe Wang, Wei Wu, Shigeki Tomishima
, Patrick Stolt, Shih-Lien Lu:
23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cache. ISSCC 2017: 404-405 - [c5]Tsung-Fu Hsieh, Jin-Fu Li, Kuan-Te Wu, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, Yung-Fa Chou:
Software-hardware-cooperated built-in self-test scheme for channel-based DRAMs. ITC-Asia 2017: 107-111 - 2015
- [c4]Chi-Chun Yang, Jin-Fu Li, Yun-Chao Yu, Kuan-Te Wu, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou:
A hybrid built-in self-test scheme for DRAMs. VLSI-DAT 2015: 1-4 - 2014
- [c3]Yun-Chao You, Chi-Chun Yang, Jin-Fu Li, Chih-Yen Lo, Chao-Hsun Chen, Jenn-Shiang Lai, Ding-Ming Kwai, Yung-Fa Chou, Cheng-Wen Wu:
BIST-Assisted Tuning Scheme for Minimizing IO-Channel Power of TSV-Based 3D DRAMs. ATS 2014: 1-6 - 1994
- [c2]Jenn-Shiang Lai, Sy-Yen Kuo, Ing-Yi Chen:
Neural Networks for Optimization Problems in Graph Theory. ISCAS 1994: 269-272 - 1993
- [c1]Jenn-Shiang Lai, Young-Ja Ko, Sy-Yen Kuo:
Artificial Neural Networks for the Bipartite and K-partite Subgraph Problems. PARLE 1993: 426-437
Coauthor Index
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