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ORCIDChirag Ravishankar
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2020 – today
- 2023
[c12]Abhishek Kumar Jain, Chirag Ravishankar, Hossein Omidian, Sharan Kumar, Maithilee Kulkarni, Aashish Tripathi, Dinesh Gaitonde:
Modular and Lean Architecture with Elasticity for Sparse Matrix Vector Multiplication on FPGAs. FCCM 2023: 133-143- [c11]Shashwat Shrivastava
, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic:
Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing. FPGA 2023: 231 - [c10]Shashwat Shrivastava, Stefan Nikolic, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic:
IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck. ICCAD 2023: 1-9
2010 – 2019
- 2019
- [c9]Brian Gaide, Dinesh Gaitonde, Chirag Ravishankar, Trevor Bauer:
Xilinx Adaptive Compute Acceleration Platform: VersalTM Architecture. FPGA 2019: 84-93 - 2018
- [c8]Chirag Ravishankar, Dinesh Gaitonde, Trevor Bauer:
Placement Strategies for 2.5D FPGA Fabric Architectures. FPL 2018: 16-20 - [c7]Chirag Ravishankar, Henri Fraisse, Dinesh Gaitonde:
SAT Based Place-And-Route for High-Speed Designs on 2.5D FPGAs. FPT 2018: 118-125 - 2012
- [j2]Chirag Ravishankar, Jason Helge Anderson, Andrew A. Kennings:
FPGA Power Reduction by Guarded Evaluation Considering Logic Architecture. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(9): 1305-1318 (2012) - [j1]Jason Helge Anderson, Qiang Wang, Chirag Ravishankar:
Raising FPGA Logic Density Through Synthesis-Inspired Architecture. IEEE Trans. Very Large Scale Integr. Syst. 20(3): 537-550 (2012) - [c6]Sundaram Ananthanarayanan, Chirag Ravishankar, Siddharth Garg, Andrew A. Kennings:
EmPower: FPGA based emulation of dynamic power management algorithms for multi-core systems on chip (abstract only). FPGA 2012: 266 - [c5]Chirag Ravishankar, Sundaram Ananthanarayanan, Siddharth Garg, Andrew A. Kennings:
EmPower: FPGA based rapid prototyping of dynamic power management algorithms for multi-processor systems on chip. FPL 2012: 41-48 - [c4]Chirag Ravishankar, Sundaram Ananthanarayanan, Siddharth Garg, Andrew A. Kennings:
Analysis and evaluation of greedy thread swapping based dynamic power management for MPSoC platforms. ISQED 2012: 617-624 - [c3]Chirag Ravishankar, Andrew A. Kennings, Jason Helge Anderson:
FPGA power reduction by guarded evaluation considering physical information. VLSI-SoC 2012: 271-274 - 2011
- [c2]Andrew A. Kennings, Chirag Ravishankar:
Parallel FPGA technology mapping using multi-core architectures. CCECE 2011: 274-279 - 2010
- [c1]Jason Helge Anderson, Chirag Ravishankar:
FPGA power reduction by guarded evaluation. FPGA 2010: 157-166
Coauthor Index
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