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ORCID33rd FCCM 2025: Fayetteville, AR, USA
- 33rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2025, Fayetteville, AR, USA, May 4-7, 2025. IEEE 2025, ISBN 979-8-3315-0281-2
- Jason Sinaga, Shay Snyder, Md. Abdullah-Al Kaiser, Dan Jinoy, Gregory Schwartz, Maryam Parsa, Akhilesh Jaiswal:
Reconfigurable Retina-Inspired Looming Detection. 1-7 - Ruiqi Chen
, Yangxintong Lyu, Han Bao, Jiayu Liu, Yanxiang Zhu, Shidi Tang, Ming Ling, Bruno da Silva:
FPGA-Based Approximate Multiplier for FP8. 1-9 - Dilshan Kumarathunga, Qilin Hu, Zhenman Fang:
AutoNTT: Automatic Architecture Design and Exploration for Number Theoretic Transform Acceleration on FPGAs. 1-9 - Yankun Zhu, Ranxi Lin, Pingqiang Zhou:
Defending Side-Channel Attacks in Convolutional Neural Networks with Channel-Level Parallelization. 1 - Jiho Kim, Cong Hao:
RealProbe: An Automated and Lightweight Performance Profiler for In-FPGA Execution of High-Level Synthesis Designs. 10-18 - Chengyue Wang, Jiahao Zhang, Yingquan Wu, Jason Cong:
HP-FFT: A General High-Performance FFT Generator Using High-Level Synthesis. 19-23 - Chaital G. Sathe, Yiorgos Makris, Benjamin Carrion Schafer:
FREEDOM: FPGA-Based Hardware Redaction Emulator. 24-28 - Canberk Sönmez, Mohamed Shahawy, Paolo Ienne:
HBMex: An Attachment for Nonbursting Accelerators to Enhance HBM Performance. 29-37 - Yang Yang, Rajgopal Kannan, Viktor K. Prasanna:
High Throughput Matrix Transposition on HBM-Enabled FPGAs. 38-46 - Martin Langhammer, George A. Constantinides:
Banked Memories for Soft SIMT Processors. 47-55 - Giuseppe Sorrentino, Paolo Salvatore Galfano, Eleonora D'Arnese, Davide Conficconi:
Soaring with TRILLI: An HW/SW Heterogeneous Accelerator for Multi-Modal Image Registration. 56-65 - Dimitrios Gourounas, Austin G. James, Bagus Hanindhito, Arash Fathi, Lizy K. John, Andreas Gerstlauer:
HighWave: Large-Scale High-Bandwidth Wave Simulations on FPGAs. 66-74 - Sachini Wickramasinghe, Yi-Chien Lin, Cauligi S. Raghavendra, Viktor K. Prasanna:
SMART: High-Performance SAR ATR Through Model-Architecture Co-Design on FPGA. 75-84 - Erika Hunhoff, Joseph Melber, Kristof Denolf, Andra Bisca, Samuel Bayliss, Stephen Neuendorffer, Jeff Fifield, Jack Lo, Pranathi Vasireddy, Phil James-Roxby, Eric Keller:
Efficiency, Expressivity, and Extensibility in a Close-to-Metal NPU Programming Interface. 85-94 - Johannes Menzel, Christian Plessl:
Efficient and Distributed Computation of Electron Repulsion Integrals on AMD AI Engines. 95-104 - Zakary Nafziger, Steven J. E. Wilton:
Chronbench: An Incremental HDL Benchmark Suite. 105-113 - Yinting Huang, Keran Zheng, Zhewen Yu, Christos-Savvas Bouganis:
ITERA-LLM: Boosting Sub-8-Bit Large Language Model Inference via Iterative Tensor Decomposition. 114-122 - Zifan He, Anderson Truong, Yingqi Cao, Jason Cong:
InTAR: Inter-Task Auto-Reconfigurable Accelerator Design for High Data Volume Variation in DNNs. 123-132 - Zixi Zhang, Balint Szekely, Pedro Gimenes, Greg Chadwick, Hugo McNally, Jianyi Cheng, Robert D. Mullins, Yiren Zhao:
LLM4DV: Using Large Language Models for Hardware Test Stimuli Generation. 133-137 - Chihyo Ahn, Ruobing Han, Udit Subramanya, Jisheng Zhao, Blaise Tine, Hyesoon Kim:
SoftCUDA: Running CUDA on Softcore GPU. 138-142 - Shashwat Shrivastava, Stefan Nikolic, Sun Tanaka, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic:
Guaranteed Yet Hard to Find: Uncovering FPGA Routing Convergence Paradox. 143-151 - Suyash Vardhan Singh, Iftakhar Ahmad, David Andrews, Miaoqing Huang, Austin R. J. Downey, Jason D. Bakos:
N-TORC: Native Tensor Optimizer for Real-Time Constraints. 152-161 - Huifeng Ke, Sihao Liu, Licheng Guo, Zifan He, Linghao Song, Suhail Basalama, Yuze Chi, Tony Nowatzki, Jason Cong:
NoH: NoC Compilation in High-Level Synthesis. 162-171 - Mahesh A. Iyer, Andrew B. Kahng, Jason Luu, Bodhisatta Pramanik, Kristofer Vorwerk, Grace Zgheib:
A Partitioning-Based CAD Flow for Interposer-Based Multi-Die FPGAs. 172-180 - Yiyue Jiang, John Dooley, Aidan Edward Colgan, Jonathan Guimaraes Ribeiro, Zhilin Ren, Miriam Leeser:
Transfer Learning on the Edge for a Wireless Application Using an SoC Platform. 181-188 - Alessandro Verosimile, Francesco Peverelli, Marco D. Santambrogio:
Moyogi: A Memory-Centric Accelerator for Low-Latency Random Forest Inference on Embedded Devices. 189-197 - Alexandra Zhang Jiang, Jonathan Ta, Yuqiao Li, Zhou Li, Nalini Venkatasubramanian, Monica D. Kohler, Sang-Woo Jun:
IceSpy: Reconfigurable Edge Accelerator for Scalable and Private Structural Health Monitoring. 198-207 - Marta Andronic, George A. Constantinides:
NeuraLUT-Assemble: Hardware-Aware Assembling of Sub-Neural Networks for Efficient LUT Inference. 208-216 - Kailing Zhou, Han Jiao, Wenjin Huang, Yihua Huang:
An Efficient FPGA-Based Hardware Accelerator of Fully Quantized Mamba-2. 217-226 - Minghan Jiang, Yonggen Li, Rui Xiao, Haibin Shen, Kejie Huang:
A FeFET-Based Compute-in-Memory Architecture on FPGA for Neural Network Inference. 236-242 - Aman Arora:
Compute-In-Memory on FPGAs for Deep Learning: A Review. 243-253 - Houxuan Guo, Manuel Blanco Valentin, Xiuyuan He, Seda Ogrenci:
Toward Reconfigurable In-Pixel Computing: A Fault-Tolerant Design Flow for Machine Learning Accelerators: (Invited Paper). 261-267 - Shuyang Li, Hanqing Zhang, Ruiqi Chen, Bruno da Silva, Giorgian Borca-Tasciuc, Dantong Yu, Cong Hao:
TrackGNN: A Highly Parallelized and Self-Adaptive GNN Accelerator for Track Reconstruction on FPGAs. 269 - Binglei Lou, Ruilin Wu, Philip Leong:
SparseLUT: Sparse Connectivity Optimization for Lookup Table-Based Deep Neural Networks. 270 - André Rösti, Michael Franz:
Unlocking the AMD Neural Processing Unit for ML Training on the Client Using Bare-Metal-Programming Tools. 271 - Jiacheng Cao, Jiaqi Guo, Wei Xiong, Huanlin Luo, Jian Wang, Jinmei Lai:
An Energy-Efficient FPGA-Based Vision Transformer Accelerator via Software-Hardware Co-Design. 272 - Siyuan Miao, Lingkang Zhu, Chen Wu, Shaoqiang Lu, Jinming Lyu, Lei He:
C2OPU: Hybrid Compute-in-Memory and Coarse-Grained Reconfigurable Architecture for Overlay Processing of Transformers. 273 - Victor Agostinelli, Nicolas Bohm Agostini, Antonino Tumeo:
UltraFormer: An Efficient Transformer for FPGAs. 274 - Can Xiao, Jianyi Cheng, Aaron Zhao:
Microscaling Vision Transformers on FPGAs. 275 - Yuhao Liu, Salim Ullah, Akash Kumar:
BiKA: Binarized KAN-inspired Neural Network for Efficient Hardware Accelerator Designs. 276 - Yilun Xu, Abhi D. Rajagopala, Neelay Fruitwala, Gang Huang:
Multi-FPGA Synchronization and Data Communication for Quantum Control and Measurement. 277 - Wanzheng Weng, Pingqiang Zhou:
RapidPnR: Accelerating the Physical Design for FPGAs via Design-Level Parallelism. 278 - Peifang Zhou, Bachir Berkane, Vlad Druz, Mark Rollins:
A High-Throughput Implementation of the MUSIC Algorithm Using AMD Versal AI Engine. 279 - Yiming Gao, Herman Lam:
APR-OIS: A Near-Sensor Point Cloud Pre-Processing Accelerator on FPGA. 280 - Ehsan Kabir, Austin R. J. Downey, Jason D. Bakos, David Andrews, Miaoqing Huang:
Optimized Coding and Parameter Selection for Efficient FPGA Design of Attention Mechanisms. 281 - Tiago Santos, João Bispo, João M. P. Cardoso, James C. Hoe:
On Improving the HLS Compatibility of Large C/C++ Code Regions. 282 - Manuel de Castro, Roberto R. Osorio, Yuri Torres, Diego R. Llanos:
Accelerating Scientific Model Optimization with a Pipelined FPGA-Based Differential Evolution Engine. 283 - Zhaoqi Wang, Peter Mbua, Christophe Bobda:
ASTEF: FPGA-Based Enhancement of Event Camera Performance in Low-Light Conditions. 284 - Huachen Zhang, Jianyang Ding, Bowen Jiang, Tianshuo Lu, Wei Xu, Zhilei Chai:
RV-ESMC: Efficient Sparse Matrix Convolution Processor based on RISC-V Custom instructions for Edge Platforms. 285 - Tianshuo Lu, Jianyang Ding, Huachen Zhang, Bowen Jiang, Wei Xu, Zhilei Chai:
EVO-QNN: Efficient Mixed-Precision Quantization Inference on RISC-V-Based Edge Device. 286 - Menzo Bouaissi, Paolo Ienne, Lana Josipovic, Andrea Guerrieri:
DRSA: Accelerating Macro Placement on Commercial FPGAs. 287 - Alexandre Ortega, Lilian Bossuet, Brice Colombier:
Low-Latency FFT/iFFT RTL Implementation for the FALCON Post-Quantum Signature Algorithm. 288 - Farzad Razi, Mehran Shoushtari Moghadam, M. Hassan Najafi, Sercan Aygun, Marc D. Riedel:
Breaking New Ground: Division Directly in Memory. 289 - Archit Gajjar, Lei Zhao, Omar Eldash, Aishwarya Natarajan, Xia Sheng, Giacomo Pedretti, Aman Arora, Paolo Faraboschi, Jim Ignowski, Luca Buonanno:
Analog In-Memory Computing Enhanced FPGA for High-Throughput and Energy-Efficient Acceleration. 290 - Andrew Dervay, Omar Al Kailani, Wenfeng Zhao:
BCIM: A Bit-Serial Approach for Block-Cipher-in-Memory. 291 - Deepak Vungarala, Md Hasibul Amin, Pietro Mercati, Arman Roohi, Ramtin Zand, Shaahin Angizi:
LLM-IMC: Automating Analog In-Memory Computing Architecture Generation with Large Language Models. 292 - Hyun Woo Oh, Hanning Chen, Sanggeon Yun, Yang Ni, Behnam Khaleghi, Fei Wen, Mohsen Imani:
A Multimodal AI Acceleration with Dynamic Pruning and Run-Time Configuration. 293 - Saleen Bhattarai, Edwin Peters, Sean O'Byrne, David Petty:
Performance Modeling and Comparisons of an FPGA-based Direct Simulation Monte Carlo Solver. 294 - Hemanth Ramesh, Naarayanan Rao VSathish, Edson Horta, Antonio Barbalace, Binoy Ravindran:
SmartNIC-Based Distributed Shared Memory. 295 - Sepehr Tabrizchi, Shaahin Angizi, Arman Roohi:
iSEW: in-Sensor Embedded Watermarking for Secure Imaging. 296 - Philippos Papaphilippou, Wayne Luk, David Gregg:
Efficient Adaptable Streaming Aggregation Engine. 297 - Jinming Zhuang, Peipei Zhou:
Ph.D. Project ARIES: Efficient Mapping and Automated Compilation for AMD Versal Devices. 298-299 - Hang Gu, Teng Wang, Chao Wang:
Ph.D. Project: An Efficient NTT Accelerator Supporting Various Lengths for HHE. 300-301 - Haoran Xue, Teng Wang, Chao Wang:
Ph.D. Project: Floorplan Quality Prediction for HLS Design Exploration on Multi-Die FPGA. 302-303 - Xingyan Chen, Lei Gong, Chao Wang:
Ph.D. Project: A Novel Compilation-Based Approach for Generating Sparse Tensor Accelerators. 304-305 - Marta Andronic, George A. Constantinides:
Ph.D. Project Hardware-Aware Neural Networks. 306-307 - Tiago Santos, João Bispo, João M. P. Cardoso:
Ph.D. Project: Holistic Partitioning and Optimization of CPU-FPGA Applications Through Source-to-Source Compilation. 308-309 - Zhuoping Yang, Peipei Zhou:
Ph.D. Project AIM: Accelerating Arbitrary-Precision Integer Multiplication on Heterogeneous Reconfigurable Computing Platform Versal ACAP. 310-311
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