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2010 – 2019
- 2013
[j3]Matthew R. Guthaus, Gustavo Wilke, Ricardo Reis
:
Revisiting automated physical synthesis of high-performance clock networks. ACM Trans. Design Autom. Electr. Syst. 18(2): 31:1-31:27 (2013)- 2012
- [j2]Matthew R. Guthaus, Xuchu Hu, Gustavo Wilke, Guilherme Flach, Ricardo Reis:
High-performance clock mesh optimization. ACM Trans. Design Autom. Electr. Syst. 17(3): 33:1-33:17 (2012) - [c14]Gracieli Posser, Guilherme Flach, Gustavo Wilke, Ricardo Reis:
Transistor sizing and gate sizing using geometric programming considering delay minimization. NEWCAS 2012: 85-88 - 2011
- [c13]Gracieli Posser, Guilherme Flach, Gustavo Wilke, Ricardo Reis:
Gate Sizing Minimizing Delay and Area. ISVLSI 2011: 315-316 - 2010
- [j1]Sandro Sawicki, Gustavo Wilke, Marcelo O. Johann, Ricardo Reis:
3D-Via Driven Partitioning for 3D VLSI Integrated Circuits. CLEI Electron. J. 13(3) (2010) - [c12]Matthew R. Guthaus, Gustavo Wilke, Ricardo Reis:
Non-uniform clock mesh optimization with linear programming buffer insertion. DAC 2010: 74-79 - [c11]Gracieli Posser, Adriel Ziesemer, Daniel Guimares Jr., Gustavo Wilke, Ricardo A. L. Reis:
A study on layout quality of automatic generated cells. ICECS 2010: 651-654 - [c10]Guilherme Flach, Gustavo Wilke, Marcelo O. Johann, Ricardo Reis:
A Mesh-Buffer Displacement Optimization Strategy. ISVLSI 2010: 282-287 - [c9]Gustavo Wilke, Ricardo Reis:
Variability-aware physical design techniques. LATW 2010: 1
2000 – 2009
- 2009
- [c8]Sandro Sawicki, Gustavo Wilke, Marcelo O. Johann, Ricardo Reis:
A cells and I/O pins partitioning refinement algorithm for 3D VLSI circuits. ICECS 2009: 852-855 - 2008
- [c7]Gustavo Wilke, Ricardo Reis:
A New Clock Mesh Buffer Sizing Methodology for Skew and Power Reduction. ISVLSI 2008: 227-232 - [c6]Gustavo Wilke, Renan Fonseca, Cecilia Mezzomo, Ricardo Reis:
A novel scheme to reduce short-circuit power in mesh-based clock architectures. SBCCI 2008: 117-122 - 2003
- [c5]David Guerrero Martos, Gustavo Wilke, José Luís Almada Güntzel, Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Alejandro Millán:
Computational Delay Models to Estimate the Delay of Floating Cubes in CMOS Circuits. PATMOS 2003: 501-510 - [c4]Daniel Lima Ferrão, Gustavo Wilke, Ricardo Augusto da Luz Reis, José Luís Almada Güntzel:
Improving Critical Path Identification in Functional Timing Analysis. SBCCI 2003: 297-302 - [c3]Cristiano Santos, Gustavo Wilke, Cristiano Lazzari, Ricardo Reis, José Luís Almada Güntzel:
A Transistor Sizing Method Applied to an Automatic Layout Generation Tool. SBCCI 2003: 303- - 2002
- [c2]José Luís Güntzel, Gustavo Wilke, Márcio Bystronski, Ana Cristina Medina Pinto, Ricardo Reis:
A Comparison Between Testability Measures Applied to Complex Gates. LATW 2002: 144-149 - [c1]Gustavo Wilke, José Luís Güntzel, Márcio Bystronski, Ana Cristina Medina Pinto, Ricardo Reis:
Finding the Critical Delay of Combinational Blocks by Floating Vector Simulation and Path Tracing. SBCCI 2002: 277-282
Coauthor Index
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