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E. George Walters III

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affiliation: Penn State Erie, PA, USA

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2010 – 2019

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2016
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E. George Walters III:
Array Multipliers for High Throughput in Xilinx FPGAs with 6-Input LUTs. Comput. 5(4): 20 (2016)
2015
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E. George Walters III:
Linear and Quadratic Interpolators Using Truncated-Matrix Multipliers and Squarers. Comput. 4(4): 293-321 (2015)
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E. George Walters III:
24-bit significand multiplier for FPGA floating-point multiplication. ACSSC 2015: 717-721
2014
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E. George Walters III:
Partial-product generation and addition for multiplication in FPGAs with 6-input LUTs. ACSSC 2014: 1247-1251
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Masoud Sadeghian, James E. Stine, E. George Walters III:
Optimized cubic chebyshev interpolator for elementary function hardware implementations. ISCAS 2014: 1536-1539
2012
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E. George Walters III:
FPGA-accelerated simulation of truncated-matrix multipliers. ACSCC 2012: 993-997
2011
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E. George Walters III, Michael J. Schulte:
Truncated-matrix multipliers with coefficient shifting. ACSCC 2011: 176-180

2000 – 2009

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2005
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E. George Walters III, Michael J. Schulte:
Efficient Function Approximation Using Truncated Multipliers and Squarers. IEEE Symposium on Computer Arithmetic 2005: 232-239
2003
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Michael J. Schulte, Louis Marquette, Shankar Krithivasan, E. George Walters III, John Glossner:
Combined Multiplication and Sum-of-Squares Units. ASAP 2003: 204-214

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