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ORCIDSunil D. Sherlekar
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2010 – 2019
- 2012
[c19]Sunil D. Sherlekar:
Parallel Computing Goes Mainstream. IC3 2012: 4-5- [c18]Sunil D. Sherlekar:
Intel Many Integrated Core (MIC) Architecture. ICPADS 2012: 947
2000 – 2009
- 2003
- [j8]Sunil D. Sherlekar, Rajeev Prasad:
A Global Access Independent Billing Model: Users' Perspective. Wirel. Pers. Commun. 26(2-3): 169-178 (2003) - 2000
- [c17]Mahesh Mehendale, Sunil D. Sherlekar:
Power Reduction Techniques for Portable DSP Applications. VLSI Design 2000: 3
1990 – 1999
- 1999
- [c16]Mahesh Mehendale, Sunil D. Sherlekar:
Low Power Code Generation of Multiplication-free Linear Transforms. VLSI Design 1999: 42-47 - 1998
- [j7]Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh:
Low-power realization of FIR filters on programmable DSPs. IEEE Trans. Very Large Scale Integr. Syst. 6(4): 546-553 (1998) - [c15]Mahesh Mehendale, Amit Sinha, Sunil D. Sherlekar:
Low Power Realization of FIR Filters Implemented using Distributed Arithmetic. ASP-DAC 1998: 151-156 - [c14]Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh:
Algorithmic and Architectural Transformations for Low Power Realization of FIR Filters. VLSI Design 1998: 12-17 - [c13]Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh:
Extensions to Programmable DSP architectures for Reduced Power Dissipation. VLSI Design 1998: 37- - [c12]Mahesh Mehendale, Somdipta Basu Roy, Sunil D. Sherlekar, G. Venkatesh:
Coefficient Transformations for Area-Efficient Implementation of Multiplier-less FIR Filters. VLSI Design 1998: 110-115 - 1997
- [c11]Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh:
Area-Delay Tradeoff in Distributed Arithmetic Based Implementation of FIR Filters. VLSI Design 1997: 124-129 - 1996
- [j6]Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar:
Monitoring machine based synthesis technique for concurrent error detection in finite state machines. J. Electron. Test. 8(2): 179-201 (1996) - [c10]Mahesh Mehendale, G. Venkatesh, Sunil D. Sherlekar:
Optimized Code Generation of Multiplication-free Linear Transforms. DAC 1996: 41-46 - [c9]Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh:
Low power realization of FIR filters using multirate architectures. VLSI Design 1996: 370-375 - 1995
- [j5]Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar:
Concurrent Error Detection Using Monitoring Machines. IEEE Des. Test Comput. 12(3): 24-32 (1995) - [c8]Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh:
Techniques for low power realization for FIR filters. ASP-DAC 1995 - [c7]Mahesh Mehendale, Sunil D. Sherlekar, G. Venkatesh:
Synthesis of multiplier-less FIR filters with minimum number of additions. ICCAD 1995: 668-671 - [c6]B. Ravi Kishore, Rubin A. Parekhji, Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh:
A new methodology for the design of low-cost fail safe circuits and networks. VLSI Design 1995: 355-358 - 1993
- [c5]Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar:
State Assignment for Optimal Design of Monitored Self-Checking Sequential Circuits. VLSI Design 1993: 15-20 - [c4]Sunil D. Sherlekar:
Export of VLSI Design and CAD: Present and Future. VLSI Design 1993: 264 - 1992
- [j4]Ajay Khoche, Sunil D. Sherlekar, G. Venkatesh, Raja Venkateswaran:
A Behavioral Fault Simulator for Ideal. IEEE Des. Test Comput. 9(4): 14-21 (1992) - [c3]Yogesh Mishra, Sunil D. Sherlekar, G. Venkatesh:
Path breaker: a tool for the optimal design of speed independent asynchronous controllers. EURO-DAC 1992: 2-8 - [c2]Ajay Khoche, Sunil D. Sherlekar, G. Venkatesh:
A Behavioral Fault Simulator For Ideal. VLSI Design 1992: 137-143 - 1991
- [j3]Sandeep Pagey, Sunil D. Sherlekar, G. Venkatesh:
A methodology for the design of SFS/SCD circuits for a class of unordered codes. J. Electron. Test. 2(3): 261-277 (1991) - [c1]Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar:
A Methodology for Designing Optimal Self-Checking Sequential Circuits. ITC 1991: 283-291
1980 – 1989
- 1989
- [j2]Alok Kumar, Vijeta Kashyap, Sunil D. Sherlekar, G. Venkatesh, S. Biswas, Anshul Kumar, P. C. P. Bhatt, Sashi Kumar:
Ideas: a tool for VLSI CAD. IEEE Des. Test 6(5): 50-57 (1989) - 1988
- [j1]Sunil D. Sherlekar, P. S. Subramanian:
Conditionally robust two-pattern tests and CMOS design for testability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(3): 325-332 (1988)
Coauthor Index
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