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ORCIDITC 1991: Nashville, TN, USA
- Proceedings IEEE International Test Conference 1991, Test: Faster, Better, Sooner, Nashville, TN, USA, October 26-30, 1991. IEEE Computer Society 1991, ISBN 0-8186-9156-5
Session 1: Plenary
Keynote Address
- Phil Robinson:
Concurrent Engineering: Creating Designs That Are Faster, Better and Available Sooner. ITC 1991: 19
Session 2: Practical BIST Implementation Case Studies
- Sudha Sarma:
Built-In Self-Test Considerations in a High-Performance, General-Purpose Processor. 21-27 - Paul H. Bardell, Michael J. Lapointe:
Production Experience with Built-In Self-Test in the IBM ES/9000 System. 28-36 - Richard Illman, Terry Bird, George Catlow, Stephen Clarke, Len Theobald, Gil Willetts:
Built-In Self-Test of the VLSI Content Addressable Filestore. 37-46 - Charles E. Stroud:
Built-In Self-Test for High-Speed Data-Path Circuitry. 47-56
Session 3: Sequential ATPG
- Thomas Kropf, Hans-Joachim Wunderlich:
A Common Approach to Test Generation and Hardware Verification Based on Temporal Logic. 57-66 - Hyunwoo Cho, Gary D. Hachtel, Fabio Somenzi:
Fast Sequential ATPG Based on Implicit State Enumeration. 67-74 - Toshinobu Ono, Masaaki Yoshida:
A Test Generation Method for Sequential Circuits Based on Maximum Utilization of Internal States. 75-82 - Tsu-Wei Ku, Wei-Kong Chia:
A Sequential Test Generator with Explicit Elimination of Easy-to-Test Faults. 83-87
Session 4: Boundary Scan: Test and Diagnostics of the Infrastructure
- Mark F. Lefebvre:
Test Generation: A Boundary Scan Implementation for Module Interconnect Testing. 88-95 - Jung-Cheun Lien, Melvin A. Breuer:
Maximal Diagnosis for Wiring Networks. 96-105 - Frans G. M. de Jong, Frank van der Heyden:
Testing the Integrity of the Boundary Scan Test Infrastructure. 106-112 - Kenneth E. Posse:
A Design-for-Testability Architecture for Multichip Modules. 113-121
Session 5: Case Studies in VLSI Chip Testing
- Jose A. Lyon, Mike Gladden, Eytan Hartung, Eric Hoang, K. Raghunathan:
Testability Features of the 68HC16Z1. 122-130 - Pierre Thorel, Jean-Luc Rainard, Alain Botta, Alain Chemarin, Jacques Majos:
Implementing Boundary-Scan and Pseudo-Random BIST in an Asynchronous Transfer Mode Switch. 131-139 - Johan Karlsson, Ulf Gunneflo, Peter Lidén, Jan Torin:
Two Fault Injection Techniques for Test of Fault Handling Mechanisms. 140-149 - Tony Cheng, Eric Hoang, David Rivera, Alan Haedge, Jamie Fontenot, Glenn Carson:
Test Grading the 68332. 150-156
Session 6: DFT: New Algorithms for Automation Tools
- Sungho Kim, Prithviraj Banerjee, Srinivas Patil:
A Layout Driven Design for Testability Technique for MOS VLSI Circuits. 157-165 - Miron Abramovici, James J. Kulikowski, Rabindra K. Roy:
The Best Flip-Flops to Scan. 166-173 - Magdy S. Abadir, Joe Newman, Desmond D'Souza, Steve Spencer:
Partitioning Hierarchical Designs for Testability. 174-183
Session 7: Test Generation and Compaction
- John Giraldi, Michael L. Bushnell:
Search State Equivalence for Redundancy Identification and Test Generation. 184-193 - Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy:
COMPACTEST: A Method to Generate Compact Test Sets for Combinatorial Circuits. 194-203 - Gert-Jan Tromp:
Minimal Test Sets for Combinatorial Circuits. 204-209
Session 8: Using Test Results for Process Improvement
- Dharam Vir Das, Sharad C. Seth, Vishwani D. Agrawal:
Estimating the Quality of Manufactured Digital Sequential Circuits. 210-217 - Eric Bruls, F. Camerik, H. J. Kretschman, Jochen A. G. Jess:
A Generic Method to Develop a Defect Monitoring System for IC Processes. 218-227 - Adit D. Singh, C. Mani Krishna:
On Optimizing Wafer-Probe Testing for Product Quality Using Die-Yield Prediction. 228-237
Session 9: Contactless Probing
- M. Marzouki, J. Laurent, Bernard Courtois:
Coupling Electron-Beam Probing with Knowledge-Based Fault Localization. 238-247 - Rafic Z. Makki, Kasra Daneshvar, Farid Tranjan, Richard Greene:
On the Integration of Design and Manufacturing for Improved Testability. 248-255 - Klaus Helmreich, Peter Nagel, Werner Wolz, Klaus D. Müller-Glaser:
An Approach to Chip-Internal Current Monitoring and Measurement Using an Electron Beam Tester. 256-262
Session 10: DFT: Advanced Design and Analysis Techniques
- Bong-Hee Park, Premachandran R. Menon:
Robustly Scan-Testable CMOS Sequential Circuits. 263-272 - Irith Pomeranz, Sudhakar M. Reddy:
Achieving Complete Delay Fault Testability by Extra Inputs. 273-282 - Rubin A. Parekhji, G. Venkatesh, Sunil D. Sherlekar:
A Methodology for Designing Optimal Self-Checking Sequential Circuits. 283-291
Session 11: Physical Defects and Analysis 1
- Hong Hao, Edward J. McCluskey:
"Resistive Shorts" Within CMOS Gates. 292-301 - Christopher L. Henderson, Jerry M. Soden, Charles F. Hawkins:
The Behavior and Testing Implications of CMOS IC Logic Gate Open Circuits. 302-310 - Thomas M. Storey, Wojciech Maly, John Andrews, Myron Miske:
Stuck Fault and Current Testing Comparison Using CMOS Chip Test. 311-318
Session 12: Computer Assisted Diagnosis and Repair
- John McWha, Peter Kouklamanis:
A Product Information Access System for the Verification, Test, Diagnosis and Repair of Electronic Assemblies. 319-326 - Vijay Pitchumani, Pankaj Mayor, Nimish Radia:
Fault Diagnosis using Functional Fault Models for VHDL descriptions. 327-337 - Gordon F. Taylor, Steven M. Blumenau:
A Pragmatic Test Data Management System. 338-344
Session 13: Specialized Quality Topics
- Scott A. Erjavic:
Characterization and Control of PLCC and MQFP Lead Inspection Systems. 345-353 - E. Weis, E. Kinsbron, M. Snyder, B. Vogel, N. Croitoru:
Electromigration Effects in VLSI Due to Various Current Types. 354-357 - Peter C. Maxwell, Robert C. Aitken, Vic Johansen, Inshen Chiang:
The Effect of Different Test Sets on Quality Level Prediction: When is 80% better than 90%? 358-364
Session 14: Scan Design: Innovations and Enhancements
- Bulent I. Dervisoglu, Gayvin E. Stong:
Design for Testability: Using Scanpath Techniques for Path-Delay Test and Measurement. 365-374 - Jens Leenstra, Lambert Spaanenburg:
Hierarchical Test Program Development for Scan Testable Circuits. 375-384 - Sean P. Morley, Ralph Marlett:
Selectable Length Partial Scan: A Method to Reduce Vector Length. 385-392
Session 15: Delay Faults and Bridging Faults
- Ankan K. Pramanick, Sudhakar M. Reddy:
On Multiple Path Propagating Tests for Path Delay Faults. 393-402 - Kwang-Ting Cheng, Srinivas Devadas, Kurt Keutzer:
A Partial Enhanced-Scan Approach to Robust Delay-Fault Test Generation for Sequential Circuits. 403-410 - Steven D. Millman, James P. Garvey Sr.:
An Accurate Bridging Fault Test Pattern Generator. 411-418
Session 16: ATE Architecture and Methods
- William R. Simpson, John W. Sheppard:
An Intelligent Approach to Automatic Test Equipment. 419-425 - Gary J. Lesmeister:
A Densely Integrated High Performance CMOS Tester. 426-429 - Bryan J. Dinteman:
Arbitrary Waveform Generation with Absolute Duration Control. 430-436
Session 17: Statistics and Test - Working Together
- Sally Wilk:
Effective Implementation of Statistical Process Control in an Integrated Circuit Test Environment. 437-445 - Barbara Cole, Glen Herzog, Phung Ngo, Steven Hinkle, Peter Sherry:
Statistical Product Monitoring: A Powerful Tool for Quality Improvement. 446-453 - D. L. Smoot, Babur Mustafa Pulat:
Don't Eliminate Incoming Test - Move It. 454-462
Session 18: BIST Issues in Logic Synthesis
- LaNae J. Avra:
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths. 463-472 - Stephen Pateras, Janusz Rajski:
Cube-Contained Random Patterns and Their Applications to the Complete Testing of Synthesized Multi-Level Circuits. 473-482 - Andrzej Krasniewski:
Can Redundancy Enhance Testability? 483-491
Session 19: Physical Defects and Analysis 2
- F. Joel Ferguson, Tracy Larrabee:
Test Pattern Generation for Realistic Bridge Faults in CMOS ICs. 492-499 - José T. de Sousa, Fernando M. Gonçalves, João Paulo Teixeira:
IC Defects-Based Testability Analysis. 500-509 - Rosa Rodríguez-Montañés, Jaume A. Segura, Víctor H. Champac, Joan Figueras, J. A. Rubio:
Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS. 510-519
Session 20: Diagnosis and Repair of Complex Custom Circuits
- Stephen M. Lorusso, Paul N. Bompastore, Michael T. Fertsch:
Integrating CrossCheck Technology into the Raytheon Test Environment. 520-529 - Robert W. Bassett, Pamela S. Gillis, John J. Shushereba:
High-Density CMOS Multichip-Module Testing and Diagnosis. 530-539
Session 21: Test Techniques as Applied to Memory Devices
- Jun-ichi Miyamoto, Nobuaki Ohtsuka, Ken-ichi Imamiya, Naoto Tomita, Yumiko Iyama:
Multi-Step Stress Test for Yield Improvement of 16Mbit EPROMs with Redundancy Scheme. 540-547 - H.-D. Oberle, Peter Muhmenthaler:
Test Pattern Development and Evaluation for DRAMs with Fault Simulator RAMSIM. 548-555 - Yoshikazu Morooka, Shigeru Mori, Hiroshi Miyamoto, Michihiro Yamada:
An Address Maskable Parallel Testing for Ultra High Density DRAMs. 556-563
Session 22: Mixed Signal Test Generation Based on Fault Modeling
- Anne Meixner, Wojciech Maly:
Fault Modeling for the Testing of Mixed Integrated Circuits. 564-572 - Gerard N. Stenbakken, T. Michael Souders:
Linear Error Modeling of Analog and Mixed-Signal Devices. 573-581 - Abhijit Chatterjee:
Concurrent Error Detection in Linear Analog and Switched-Capacitor State Variable Systems Using Continuous Checksums. 582-591 - Sheng-Jen Tsai:
Test Vector Generation for Linear Analog Devices. 592-597
Session 23: CAE for IDDq Testing
- S. Wayne Bollinger, Scott F. Midkiff:
On Test Generation for Iddq Testing of Bridging Faults in CMOS Circuits. 598-607 - Evstratios Vandris, Gerald E. Sobelman:
A Mixed Functional/IDDQ Testing Methodology for CMOS Transistor Faults. 608-614 - Chun-Hung Chen, Jacob A. Abraham:
High Quality Tests for Switch-Level Circuits Using Current and Logic Test Generation Algorithms. 615-622 - Robert C. Aitken:
Fault Location with Current Monitoring. 623-632
Session 24: Board Test: The Future Is Arriving
- Kenneth D. Wagner, Thomas W. Williams:
Enhancing Board Functional Self-Test by Concurrent Sampling. 633-640 - Partha Raghavachari:
Circuit Pack BIST from System to Factory - The MCERT Chip. 641-648 - Najmi T. Jarwala, Chi W. Yau:
Achieving Board-Level BIST Using the Boundary-Scan Master. 649-658 - Charles W. Buenzli Jr., Robert Gonzalez:
A Case Study of Mixed Signal Fault Isolation: Knowledge Based vs. Decision Tree Programming. 659-664
Session 25: Algorithms and Fault Modeling for Testing Memory Devices
- Sundarar Mohan
, Pinaki Mazumder:
Fault Modeling and Testing of GaAs Static Random Access Memories. 665-674 - Manoj Franklin, Kewal K. Saluja:
An Algorithm to Test Rams for Physical Neighborhood Pattern Sensitive Faults. 675-684 - Ad J. van de Goor, P. C. M. van der Arend, Gert-Jan Tromp:
Locating Bridging Faults in Memory Arrays. 685-694 - Prawat Nagvajara, Mark G. Karpovsky:
Built-In Self-Diagnostic Read-Only-Memories. 695-703
Session 26: Test Pattern Generation Issues in BIST
- Kiyoshi Furuya, Edward J. McCluskey:
Two-Pattern Test Capabilities of Autonomous TPG Circuits. 704-711 - Wen-Ben Jone:
Defect Level Estimation of Random and Pseudorandom Testing. 712-721 - Jacob Savir, Robert F. Berry:
At-Speed Test is not Necessarily an AC Test. 722-728
Session 27: Hierarchical Test Generation
- Jaushin Lee, Janak H. Patel:
ARTEST: An Architectural Level Test Generator for Data Path Faults and Control Faults. 729-738 - Margot Karam, Régis Leveugle, Gabriele Saucier:
Hierarchical Test Generation Based on Delayed Propagation. 739-747 - Brian T. Murray, John P. Hayes:
Test Propagation Through Modules and Circuits. 748-757
Session 28: System Testing
- Marius V. A. Hâncu, Kazuhiko Iwasaki, Yuji Sato, Mamoru Sugie:
A Concurrent Test Architecture for Massively-Parallel Computers and its Error Detection Capability. 758-767 - Dilip K. Bhavsar:
An Architecture for Extending the IEEE Standard 1149.1 Test Access Port to System Backplanes. 768-776
Session 29: ATE Implementation and Application
- Barry Baril, Dan Clayson, David McCracken, Stewart Taylor:
High Performance Pin Electronics Employing GaAs IC and Hybrid Circuit Packaging Technology. 777-789 - David C. Keezer:
Real-Time Data Comparison for GigaHertz Digital Test. 790-797 - Piero Franco, Edward J. McCluskey:
Delay Testing of Digital Circuits by Output Waveform Analysis. 798-807
Session 30: Response Compaction Issues in BIST
- D. Lambidonis, André Ivanov, Vinod K. Agarwal:
Fast Signature Computation for Linear Compactors. 808-817 - Nirmal R. Saxena, Piero Franco, Edward J. McCluskey:
Refined Bounds on Signature Analysis Aliasing for Random Testing. 818-827 - Mark G. Karpovsky, Sandeep K. Gupta, Dhiraj K. Pradhan:
Aliasing and Diagnosis Probability in MISR and STUMPS Using a General Error Model. 828-839
Session 31: Testing a Higher Level of Integration
- Vijay S. Iyengar, Gopalakrishnan Vijayan:
Test Application Timing: The Unexplored Issue in AC Test. 840-847 - Gopi Ganapathy, Jacob A. Abraham:
Hardware Acceleration Alone Will Not Make Fault Grading ULSI a Reality. 848-857 - Antonio Lioy:
Looking for Functional Fault Equivalence. 858-863
Session 32: Boundary Scan - Dealing with Chip Implementation
- Dick Chiles, John DeJaco:
Using Boundary Scan Description Language in Design. 865-868 - Lee Whetsel:
An IEEE 1149.1 Based Logic/Signature Analyzer in a Chip. 869-878 - William C. Bruce, Michael G. Gallup, Grady Giles, Tom Munns:
Implementing 1149.1 on CMOS Microprocessors. 879-886
Session 33: Synthesis for Test
- Pranav Ashar, Srinivas Devadas, Kurt Keutzer:
Gate-Delay-Fault Testability Properties of Multiplexor-Based Networks. 887-896 - Eun Sei Park, Bill Underwood, Thomas W. Williams, M. Ray Mercer:
Delay Testing Quality in Timing-Optimized Designs. 897-905 - Kaushik De, Prithviraj Banerjee:
Logic Partitioning and Resynthesis for Testability. 906-915
Session 34: Concurrent BIST Design and Verification
- Mehdi Katoozi, Arnold Nordsiek:
Low Overhead Built-In Testable Error Detection and Correction with Excellent Fault Coverage. 916-925 - Lawrence P. Holmquist, Larry L. Kinney:
Concurrent Error Detection for Restricted Fault Sets in Sequential Circuits and Microprogrammed Control Units Using Convolutional Codes. 926-935 - X. Delord, Gabriele Saucier:
Formalizing Signature Analysis for Control Flow Checking of Pipelined RISC Multiprocessors. 936-945
Session 35: Fast Fault Simulation and Multiple Faults
- Hyung Ki Lee, Dong Sam Ha:
An Efficient, Forward Fault Simulation Algorithm Based on the Parallel Pattern Single Fault Propagation. 946-955 - Ken Kubiak, W. Kent Fuchs:
Multiple-Fault Simulation and Coverage of Deterministic Single-Fault Test Sets. 956-962 - Paul G. Ryan, Shishpal Rawat, W. Kent Fuchs:
Two-Stage Fault Location. 963-968
Session 36: AC Test Calibration and Accuracy
- Tai-ichi Otsuji:
A Picosecond Accuracy Timing Error Compensation Technique in TDR Measurement. 969-975 - Raymond J. Bulaga, Edward F. Westermann:
Maximizing and Maintaining AC Test Accuracy in the Manufacturing Environment. 976-985 - Eric Rosenfeld, Bradford Sumner:
DSP Calibration for Accurate Time Waveform Reconstruction. 986-993
Session 37: Software Techniques Improve Use of Test Resources 1
- R. Wade Williams:
Integrating Emulation Techniques into General Purpose ATE. 994-1003 - Don Organ:
The enVisionTM Timing Resolver. 1004-1008 - Yehuda Shiran:
Distributed Layout Verification Using Sequential Software and Standard Hardware. 1009-1015
Session 38: DFT Applications and Experience
- Sungju Park, Sheldon B. Akers:
Parity Bit Calculation and Test Signal Compaction for BIST Applications. 1016-1023 - Subir Bandyopadhyay, Bhargab B. Bhattacharya:
On the Testable Design of Bilateral Bit-Level Systolic Arrays. 1024-1033 - Yutaka Tashiro, Hironori Yamauchi, Toshihiro Minami, Tetsuo Tajiri, Yutaka Suzuki:
An Organized Firmware Verification Environment for the Programmable Image DSP. 1034-1041
Session 39: Innovations in Mixed Signal Test Equipment
- Christopher J. Hannaford:
A Computer Architecture for High Pin Count Testers. 1042-1048 - Daniel A. Rosenthal:
A 20 Bit Waveform Source for a Mixed Signal Automatic Test System. 1049-1054 - Koji Karube, Yoshiyuki Bessho, Tokuo Takakura, Keita Gunji:
Advanced Mixed Signal Testing by DSP Localized Tester. 1055-1060
Session 40: A Potpourri of Test
- M. Kanzaki, Masahiro Ishida:
Programming for Parallel Pattern Generators. 1061-1068 - S. P. Athan, David C. Keezer, J. McKinley:
High Frequency Wafer Probing and Power Supply Resonance Effects. 1069-1078
Session 41: Software Techniques Improve Use of Test Resources 2
- Michael A. Perugini:
A Flexible Approach to Test Program Cross Compilers. 1079-1086 - Arthur E. Downey:
Industry Graphic Standards and ATE Windowing Software. 1087-1095 - Timothy J. Moore:
A Workstation Environment for Boundary Scan Interconnect Testing. 1096-1103
Panel 1: Open Meeting: Languages to Support Boundary-Scan Test
- Colin M. Maunder:
Languages to Support Boundary-Scan Test. 1104 - Carol Pyron:
Representing Boundary Scan Tests with the EDIF Test View. 1105
Panel 2: Software Testing - State of the Practice
- Ted W. Gary:
Software Testing, the State of the Practice. 1106 - Edward F. Miller:
Software Testing - The State of the Practice. 1107 - A. Jefferson Offutt:
Unit Testing Versus Integration Testing. 1108-1109 - Paul D. Roddy:
Software Testing. 1110
Panel 4: Acceptance Barriers Confronting DFT and BIST
- Tushar Gheewala:
For Test Automation, Silicon is Free. 1111 - Charles E. Stroud:
Distractions in Design for Testability and Built-Is Self-Test. 1112
Panel 5: Is Burn-In Burned Out?
- Daniel J. Burns:
Military Burn-In Requirements - One Perspective. 1113 - Noel E. Donlin:
Is Burn-In Burned Out? 1114-1115 - Charles C. Packard:
Is Burn-In Burned Out? 1116
Panel 6: Quality in Test Education?
- Richard Absher:
Can Undergraduate Test Engineering Education Be "Faster, Better, Sooner?". 1117 - Charles F. Hawkins, Richard H. Williams:
EE Curriculum - Continuous Process Improvement? 1118 - Wojciech Maly:
Improving the Quality of Test Education. 1119 - Peter C. Maxwell:
The Interaction of Test and Quality. 1120 - Kenneth Rose:
Quality in Test Education? 1121
International Test Conference 1990 Best Paper
- Thomas M. Storey, Wojciech Maly:
CMOS Bridging Fault Detection. 1123-1132
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