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ORCIDEURO-DAC 1992: Hamburg, Germany
- Gerald Musgrave:
Proceedings of the conference on European design automation, EURO-DAC '92, Hamburg, Germany, September 7-10, 1992. IEEE Computer Society Press 1992, ISBN 0-8186-2780-8 - Yogesh Mishra, Sunil D. Sherlekar, G. Venkatesh:
Path breaker: a tool for the optimal design of speed independent asynchronous controllers. 2-8 - Farhad Aghadasi:
Asynchronous state machine synthesis using data driven clocks. 9-14 - Jens Sparsø
, Jørgen Staunstrup, Michael Dantzer-Sørensen:
Design of delay insensitive circuits using multi-ring structures. 15-20 - Marc Laurentin, Alain Greiner, Roland Marbot:
DESB, a functional abstractor for CMOS VLSI circuits. 22-27 - Ronald B. Stewart, Véronique Anjubault, Philippe Garcin, Jacques Benkoski:
Automatic import of custom designs into a cell-based environment using switch-level analysis and circuit simulation. 28-31 - Mark Beardslee, Bill Lin, Alberto L. Sangiovanni-Vincentelli:
Communication based logic partitioning. 32-37 - Henning Spruth, Georg Sigl:
Parallel algorithms for slicing based final placement. 40-45 - Sundarar Mohan, Pinaki Mazumder:
Wolverines: standard cell placement on a network of workstations. 46-51 - Henrik Esbensen:
A genetic algorithm for macro cell placement. 52-57 - Viraphol Chaiyakul, Allen C.-H. Wu, Daniel D. Gajski:
Timing models for high-level synthesis. 60-65 - Sanjiv Narayan, Daniel D. Gajski:
System clock estimation based on clock slack minimization. 66-71 - Champaka Ramachandran, Fadi J. Kurdahi:
Combined topological and functionality based delay estimation using a layout-driven approach for high level applications. 72-78 - M. T. L. Schaefer, W. U. Klein:
Correctness verification of concurrent controller specifications. 80-85 - Helmut E. Graeb, Claudia U. Wieser, Kurt Antreich:
Design verification considering manufacturing tolerances by using worst-caste distances. 86-91 - Timothy Kam, P. A. Subrahmanyam:
State machine abstraction from circuit layouts using BDD's: applications in verification and synthesis. 92-97 - Matthias Mutz:
Verification of digital circuits based on formal semantics of a hardware description language. 98-103 - Masaharu Imai, Jun Sato, Alauddin Alomary, Nobuyuki Hikichi:
An integer programming approach to instruction implementation method selection problem. 106-111 - A. J. W. M. ten Berg:
Flexible controlpath microarchitecture synthesis based on artificial intelligence. 112-117 - Yi-Min Jiang, Tsing-Fa Lee, TingTing Hwang, Yaun-Long Lin:
Performance-driven interconnection optimization for microarchitecture synthesis. 118-123 - Shen Lin, Ernest S. Kuh:
Transient simulation of lossy coupled transmission lines. 126-131 - Edgar Bolender, Hans Martin Lipp:
The exact solution of timing verification. 132-137 - Prathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth:
DynaTAPP: dynamic timing analysis with partial path activation in sequential circuits. 138-141 - Ayman I. Kayssi, Karem A. Sakallah:
Delay macromodels for the timing analysis of GaAs DCFL. 142-145 - Eric Felt, Edoardo Charbon, Enrico Malavasi, Alberto L. Sangiovanni-Vincentelli:
An efficient methodology for symbolic compaction of analog IC's with multiple symmetry constraints. 148-153 - Soohong Kim, Robert Michael Owens, Mary Jane Irwin:
PERFLEX: a performance driven module generator. 154-159 - Nadine Azémard, V. Bonzom, Daniel Auvergne:
P.SIZE: a sizing aid for optimized designs. 160-165 - Hamid Savoj, Mário J. Silva, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli:
Boolean matching in logic synthesis. 168-174 - Frank Buijs:
ALU synthesis from HDL descriptions to optimized multi-level logic. 175-180 - Bogdan J. Falkowski, Ingo Schäfer, Marek A. Perkowski:
Calculation of the Rademacher-Walsh spectrum from a reduced representation of Boolean functions. 181-186 - Norbert Wehn, Hans-Jürgen Herpel, Thomas Hollstein, Peter Poechmueller, Manfred Glesner:
High-level synthesis in a rapid-prototype environment for mechatronic systems. 188-193 - Peter Windirsch, Hans-Jürgen Herpel, Andreas Laudenbach, Manfred Glesner:
Application-specific microelectronics for mechatronic systems. 194-199 - Lars W. Hagen, Fadi J. Kurdahi, Champaka Ramachandran, Andrew B. Kahng:
On the intrinsic rent parameter and spectra-based partitioning methodologies. 202-208 - Thomas Pförtner, Stefan Kiefl, Reimund Dachauer:
Embedded pin assignment for top down system design. 209-214 - Klaus Glasmacher, Gerhard Zimmermann:
Chip assembly in the PLAYOUT VLSI design system. 215-221 - Kuang-Chien Chen, Jason Cong:
Maximal reduction of lookup-table based FPGAs. 224-229 - Wei Wan, Marek A. Perkowski:
A new approach to the decomposition of incompletely specified multi-output functions based on graph coloring and local transformations and its application to FPGA mapping. 230-235 - Klaus D. Müller-Glaser, Jürgen Bortolazzi, Yankin Tanurhan:
Towards a requirements definition, specification and system design environment. 238-243 - Sridhar Narayanan, Charles Njinda, Rajesh Gupta, Melvin A. Breuer:
SIESTA: a multi-facet scan design system. 246-251 - Michiel Kraak, Ralph H. J. M. Otten:
Tackling cost optimization in testable design by forward inferencing. 252-257 - Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Donatella Sciuto, Giuseppe Zaza:
A multi level testability assistant for VLSI design. 258-263 - Chuanjin Richard Shi, Janusz A. Brzozowski:
Efficient constrained encoding for VLSI sequential logic synthesis. 266-271 - Tadeusz Luba, K. Górski, Leszek B. Wronski:
ROM-based finite state machines with PLA address modifiers. 272-277 - Debaditya Mukherjee, Massoud Pedram, Melvin A. Breuer:
Minimal area merger of finite state machine controllers. 278-283 - Jens Lienig, Krishnaiyan Thulasiraman, M. N. S. Swamy:
Routing algorithms for multi-chip modules. 286-291 - Kei-Yong Khoo, Jason Cong:
A fast multilayer general area router for MCM designs. 292-297 - Takashi Shimamoto, Hidetaka Hane, Isao Shirakawa, Shuji Tsukiyama, Shoji Shinoda, Nobuyasu Yui, Nobuyuki Nishiguchi:
A distributed routing system for multilayer SOG. 298-303 - Gianpiero Cabodi, Paolo Camurati, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
Cross-fertilizing FSM verification techniques and sequential diagnosis. 306-311 - Arno Kunzmann:
Generation of deterministic test patterns by minimal basic test sets. 312-317 - Uwe Gläser, Heinrich Theodor Vierhaus:
MILEF: an efficient approach to mixed level automatic test pattern generation. 318-321 - Didier Crestani, A. Aguila, M.-H. Gentil, P. Chardon, Christian Durante:
Automatic partitioning for deterministic test. 322-325 - Peter Gutberlet, Jens Müller, Heinrich Krämer, Wolfgang Rosenstiel:
Automatic module allocation in high level synthesis. 328-333 - Julio Septién, Daniel Mozos, Francisco Tirado, Román Hermida, Milagros Fernández:
Heuristics for branch-and-bound global allocation. 334-340 - Mehrdad Nourani, Christos A. Papachristou, Yoshiyasu Takefuji:
A neural network based algorithm for the scheduling problem in high-level synthesis. 341-346 - Tetsushi Koide, Shin'ichi Wakabayashi, Noriyoshi Yoshida:
An optimal channel pin assignment with multiple intervals for building block layout. 348-353 - Deborah C. Wang, C. Bernard Shung:
Crossing distribution. 354-361 - Bernd Becker, Paul Molitor:
A performance driven generator for efficient testable conditional-sum-adders. 370-375 - Bernd Becker, Rolf Drechsler:
A time optimal robust path-delay-fault self-testable adder. 376-381 - Derek B. I. Feltham, Jitendra Khare, Wojciech Maly:
Design for testability view on placement and routing. 382-387 - Donald A. Lobo, Barry M. Pangrle:
Generating pipelined datapaths using reduction techniques to shorten critical paths. 390-395 - Haigeng Wang, Nikil D. Dutt, Alexandru Nicolau:
Harmonic scheduling of linear recurrences for digital filter design. 396-401 - Haidar Harmanani, Christos A. Papachristou, Scott Chiu, Mehrdad Nourani:
SYNTEST: an environment for system-level design for test. 402-407 - Rafael Peset Llopis, Hans G. Kerkhoff:
A fast and accurate characterization method for full-CMOS circuits. 410-415 - Jaijeet S. Roychowdhury, A. Richard Newton, Donald O. Pederson:
An exact analytic technique for simulating uniform RC lines. 416-420 - Werner Rissiek, Werner John:
A dynamic scheduling algorithm for the simulation of MOS and bipolar circuits using waveform relaxation. 421-426 - Irith Pomeranz, Lakshmi N. Reddy, Sudhakar M. Reddy:
SPADES: a simulator for path delay faults in sequential circuits. 428-435 - Bernd Becker, Ralf Hahn, Rolf Krieger:
Fast fault simulation in combinational circuits: an efficient data structure, dynamic dominators and refined check-up. 436-441 - Nagisa Ishiura, Shuzo Yajima:
Linear time fault simulation algorithm using a content addressable memory. 442-445 - Ching Ping Wu, Chung Len Lee, Wen-Zen Shen:
SEESIM - a fast synchronous sequential circuit fault simulator with single event equivalence. 446-449 - Christoph Hübel, Detlev Ruland, Ernst Siepmann:
On modeling integrated design environments. 452-458 - Gerhard Scholz, Wolfgang Wilkes:
Information modelling of folded and unfolded design. 459-464 - Sy-Yen Kuo:
Locating logic design errors via test generation and don't-care propagation. 466-471 - Sungho Kang, Stephen A. Szygenda:
New design error modeling and metrics for design validation. 472-477 - Hideo Tamamoto, Hiroshi Yokoyama, Yuichi Narita:
Random current testing for CMOS logic circuits by monitoring a dynamic power supply current. 480-485 - Udo Mahlstedt, Matthias Heinitz, Jürgen Alt:
Test generation for IDDQ testing and leakage fault detection in CMOS circuits. 486-491 - Juan Carlos López, Margarida F. Jacome, Stephen W. Director:
Design assistance for CAD frameworks. 494-499 - Michael Rumsey, Colin Farquhar:
Unifying tool, data and process flow management. 500-505 - C. A. Schot, Mattie N. Sim, Peter M. Kist:
ANT - a test harness for the NELSIS CAD system. 506-511 - Nand Kumar, Ranga Vemuri:
Finite state machine verification on MIMD machines. 514-520 - Wolf-Dieter Tiedemann:
An approach to multi-paradigm controller synthesis from timing diagram specifications. 522-527 - Clay S. Gloster Jr., Franc Brglez:
Cellular scan test generation for sequential circuits. 530-536 - Michael Pabst, Tiziano Villa, A. Richard Newton:
Experiments on the synthesis and testability of non-scan finite state machines. 537-542 - Weiwei Mao, Michael D. Ciletti:
A quantitative measure of robustness for delay fault testing. 543-549 - Daniel C. Liebisch, Adidev Jain:
JESSI COMMON FRAMEWORK Design Management: the means to configuration and execution of the design process. 552-557 - Uwe Hunzelmann, Wolfgang Wilkes, Gunter Schlageter:
Design of a tool interface for integrated CAD-environments. 558-563 - Maria Brielmann, Elisabeth Kupitz:
Representing the hardware design process by a common data schema. 564-569 - Leszek J. Opalski, M. A. Styblinski:
GOSSIP: a generic system for statistical circuit design. 572-577 - Min Huang, M. A. Styblinski:
A generic software system for drift reliability optimization of VLSI circuits. 578-583 - Eero Pajarre, Tapani Ritoniemi, T. Tenhunen:
PAR-APLAC: Parallel Circuit Analysis and Optimization. 584-589 - Hugo De Man:
Design technology research for the nineties: more of the same? 592-596 - Günter Dedié:
Challenges for CAD in computer development in the 1990s. 597-598 - Roy Davies:
Electronic System Design: tools and methodology to meet the productivity challenge. 599-600 - Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Marius Minea:
Compiling VHDL into a high-level synthesis design representation. 604-609 - A. Stoll, Jörg Biesenack, Steffen Rumler:
Flexible timing specification in a VHDL synthesis subset. 610-615 - Loganath Ramachandran, Frank Vahid, Sanjiv Narayan, Daniel D. Gajski:
Semantics and synthesis of signals in behavioral VHDL. 616-621 - O. Pulkkinen, Klaus Kronlöf:
Integration of SDL and VHDL for high-level digital design. 624-629 - B. Lutter, Wolfgang Glunz, Franz-Josef Rammig:
Using VHDL for simulation of SDL specifications. 630-635 - Alex N. D. Zamfirescu, Cary Ussery:
VHDL and fuzzy logic if-then rules. 636-641 - Stephen E. Lim, David C. Hendry, Ping F. Yeung:
Experiences and issues in VHDL-based synthesis. 646-651 - Michael Jacobsen, Wolfgang Nebel:
VHDL for high speed desktop video ICs: experience with replacement of other simulator. 652-657 - S. Amadori, P. Coerezza:
Design of complex systems with a VHDL based methodology. 658-663 - Moe Shahdad:
1992 VHDL standardization overview. 666-667 - Jacques Rouillard:
Analysis of user requirements. 668-671 - Andrew Guyler:
VHDL 1076-1992 languages changes. 672-678 - Alain Debreil, Philippe Oddo:
Synchronous design in VHDL. 680-681 - Wolfgang Ecker:
Towards a common RT-level subset of VHDL. 682 - Adam Pawlak:
Selected aspects of component modeling. 683 - J. L. Giordana:
Interest of a VHDL native environment. 684-685 - Christel Oczko, Michael W. Nitsche:
Multi-kernel simulation description within VHDL. 686 - Alain Fonkoua, Jacques Rouillard:
VHDL intermediate format standardization activity: status and trends. 687-688 - Djamel Boussebha, Norbert Giambiasi, Janine Magnier:
Temporal verification of behavioral descriptions in VHDL. 692-697 - Gabriele Umbreit:
Providing a VHDL-interface for proof systems. 698-703 - Paul L. Harper, Ken Scott:
Towards a standard VHDL synthesis package. 706-712 - Robert A. Cottrell, Kevin Nolan, Mark Brown:
VHDL analog extensions: process, issues and status. 713-717 - Wolfgang Ecker, Sabine März:
Subtype concept of VHDL for synthesis constraints. 720-725 - Christian Berthet, Jérôme Rampon, L. Sponga:
Synthesis of VHDL arrays on RAM cells. 726-731 - Vincent Olive, R. Airiau, J. M. Bergé, Anne Robert:
Using VHDL for datapath synthesis. 732-737 - David B. Bernstein, Rodney Farrow, David Charness:
Challenges in the analysis of VHDL. 740-745 - Serge Maginot:
Evaluation criteria of HDLs: VHDL compared to Verilog, UDL/I & M. 746-751 - Wolfgang Ecker, Michael Hofmeister:
The design cube: a new model for VHDL designflow representation. 752-757 - Mark Brown:
VHDL intermediate form standardization: process, issues and status. 758-762
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