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Siddika Berna Örs Yalçin
Person information
- affiliation: Istanbul Technical University, Turkey
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2020 – today
- 2024
- [j15]Özen Özkaya
, Berna Örs:
Model-based, fully simulated, system-level power consumption estimation of IoT devices. Microprocess. Microsystems 105: 105009 (2024) - [c54]Yasin Adigüzel, Siddika Berna Örs Yalçin:
Secure Boot Design for a RISC-V Based SoC and Implementation on an FPGA. SIU 2024: 1-4 - [c53]Zülbiye Küçükömeroglu, Siddika Berna Örs Yalçin:
Model-Based Design of a Visual Cryptography Scheme and Implementation on an FPGA. SIU 2024: 1-4 - 2023
- [c52]Cagla Irmak Rumelili Koksal, Nihat Mert Cicek, Ayse Yilmazer-Metin, Berna Örs:
Lookupx: Next-Generation Quantization and Lookup Techniques for Empowering Performance and Energy Efficiency. ICECS 2023: 1-4 - [c51]Cagla Irmak Rumelili Koksal, Nihat Mert Cicek, Ayse Yilmazer-Metin, Berna Örs:
Optimizing Data Availability and Utilization in Deep Learning Accelerator SoCs. ICECS 2023: 1-4 - 2022
- [j14]Seyed Kian Mousavikia
, Erfan Gholizadehazari
, Morteza Mousazadeh
, Siddika Berna Örs Yalçin
:
Instruction Set Extension of a RiscV Based SoC for Driver Drowsiness Detection. IEEE Access 10: 58151-58162 (2022) - [j13]Latif Akçay
, Berna Örs Yalçin:
Analysing the potential of transport triggered architecture for lattice-based cryptography algorithms. Int. J. Embed. Syst. 15(5): 404-420 (2022) - [c50]Arif Burak Ordu, Mehmet Bayar, Berna Örs
:
RPL Authenticated Mode Evaluation: Authenticated Key Exchange and Network Behavioral. ICUFN 2022: 167-173 - [c49]Latif Akçay, Bartu Sürer, Berna Örs Yalçin:
Implementation of a SoC by Using lowRISC Architecture on an FPGA for Image Filtering Applications. SIU 2022: 1-4 - [c48]Canberk Tatli, Egemen Denizeri, Deniz Kumlu, Isin Erer, Berna Örs Yalçin, Furkan Isik:
Clutter Removal for Ground Penetrating Radars on FPGA: Design and Implementation. SIU 2022: 1-4 - 2021
- [j12]Latif Akçay
, Siddika Berna Örs
:
Comparison of RISC-V and transport triggered architectures for a postquantum cryptography application. Turkish J. Electr. Eng. Comput. Sci. 29(1): 321-333 (2021) - [j11]Ilker Yavuz, Berna Örs:
End-to-End Secure IoT Node Provisioning. J. Commun. 16(8): 341-346 (2021) - [c47]Özlem Altinay, Berna Örs
:
Instruction Extension of RV32I and GCC Back End for Ascon Lightweight Cryptography Algorithm. COINS 2021: 1-6 - [c46]Erfan Gholizadehazari
, Tuba Ayhan, Berna Örs
:
An FPGA Implementation of a RISC-V Based SoC System for Image Processing Applications. SIU 2021: 1-4 - [c45]Tolga Keles, Siddika Berna Örs Yalçin
, Yasar Kemal Alp:
Model Based Design of Software Defined and Cognitive Radio and Implementation on an FPGA. SIU 2021: 1-4 - [c44]Siddika Berna Örs Yalçin
, ömer Demirci, M. Murat Enes Soltekin:
Designing and Implementing Secure Automotive Network for Autonomous Cars. SIU 2021: 1-4 - [c43]Özen Özkaya, Berna Örs:
System-Level, Model-Based Power Estimation of IoT Nodes. WF-IoT 2021: 403-408 - 2020
- [c42]Elif Nur Isman, Canberk Topal, Latif Akçay, Siddika Berna Örs
:
Instruction Extension of an Open Source RV32IMC Core for NTRU Cryptosystem. ECCTD 2020: 1-5 - [e4]Siddika Berna Örs, Atilla Elçi:
SIN 2020: 13th International Conference on Security of Information and Networks, Virtual Event / Istanbul, Turkey, November 4-6, 2020. ACM 2020, ISBN 978-1-4503-8751-4 [contents] - [i1]Latif Akçay, Berna Örs Yalçin:
Comparison of RISC-V and transport triggered architectures for a post-quantum cryptography application. IACR Cryptol. ePrint Arch. 2020: 746 (2020)
2010 – 2019
- 2019
- [j10]Ahmet Aris
, Siddika Berna Örs Yalçin
, Sema F. Oktug
:
New lightweight mitigation techniques for RPL version number attacks. Ad Hoc Networks 85: 81-91 (2019) - [c41]Firat Kula
, Berna Örs
:
Average Power Consumption Estimation and Momentary Power Consumption Profile Generation of a Softcore Processor. ICDIPC 2019: 41-46 - [c40]Ersin Hatun, Gokhan Kaya, Elif Buyukkaya, Siddika Berna Örs Yalçin
:
Side Channel Analysis Using EM Radiation of RSA Algorithm Implemented on Raspberry Pi. ISNCC 2019: 1-6 - [c39]Mehmet Onur Demirtürk, Latif Akçay, Berna Örs Yalçin
:
Energy Efficient Sensor Design and Implementation on FPGA by Using Open Source Processors. SIU 2019: 1-4 - 2018
- [j9]Mehmet Tükel, Arda Yurdakul, Berna Örs
:
Customizable embedded processor array for multimedia applications. Integr. 60: 213-223 (2018) - [c38]Ersin Hatun, Elif Buyukkaya, Siddika Berna Örs Yalçin
:
Electromagnetic radiation analysis of implementation of RSA algorithm on a Raspberry Pi. SIU 2018: 1-4 - [c37]Özen Özkaya, Berna Örs
:
Model based node design methodology for secure IoT applications. SIU 2018: 1-4 - 2017
- [j8]Selahattin Gökceli
, Nikolay Zhmurov, Gunes Karabulut-Kurt
, Berna Örs
:
IoT in Action: Design and Implementation of a Building Evacuation Service. J. Comput. Networks Commun. 2017: 8595404:1-8595404:13 (2017) - [c36]Latif Akcay, Mehmet Tükel, Berna Örs
:
Design and implementation of an OpenRISC system-on-chip with an encryption peripheral. ECCTD 2017: 1-4 - 2016
- [c35]Selahattin Gökceli
, Gunes Karabulut-Kurt
, Berna Örs
:
Backhaul infrastructures in building automation systems: Wired or wireless? IDAACS-SWS 2016: 70-74 - [c34]Ahmet Aris
, Sema F. Oktug
, Siddika Berna Örs Yalçin
:
RPL version number attacks: In-depth study. NOMS 2016: 776-779 - [c33]Latif Akcay, Mehmet Tükel, Siddika Berna Örs Yalçin
:
Implementation of an OpenRISC based SoC and Linux Kernel installation on FPGA. SIU 2016: 1969-1972 - [c32]Buse Ustaoglu, Berna Örs Yalçin
:
Reliability analysis of MIPS-32 microprocessor register files designed with different fault tolerant techniques. SIU 2016: 2073-2076 - 2015
- [c31]Mehmet Akif Ozkan, Siddika Berna Örs
:
Data transmission via GSM voice channel for end to end security. ICCE-Berlin 2015: 378-382 - [c30]Buse Ustaoglu, Berna Örs Yalçin
:
Fault tolerant register file design for MIPS AES-crypto microprocessor. ICECS 2015: 442-445 - [c29]Ahmet Aris
, Sema F. Oktug
, Siddika Berna Örs Yalçin
:
Internet-of-Things security: Denial of service attacks. SIU 2015: 903-906 - [c28]Burcu Akmansayar, Salman Kurtulan
, Siddika Berna Örs
:
Design of core blocks and implementation on a programmable logic controller for a train signalization system. SIU 2015: 1942-1945 - [c27]Ahmet Cagri Bagbaba
, Berna Örs
, Osman Semih Kayhan, Ahmet Turan Erozan:
JPEG image Encryption via TEA algorithm. SIU 2015: 2090-2093 - [c26]Ahmet Turan Erozan, Ayse Siddika Aydogdu, Berna Örs
:
Application specific processor design for DCT based applications. SIU 2015: 2157-2160 - [c25]Buse Ustaoglu, Ahmet Cagri Bagbaba
, Berna Örs
, Inan Erdem:
Creating test environment with UVM for SPI. SIU 2015: 2373-2376 - [c24]Subutay Giray Baskir, Berna Örs
:
Hardware / software codesign and implementation for secure NFC applications. SIU 2015: 2392-2395 - [c23]Hasan Salih Postalli, Sercan Tuncay, Berna Örs
:
Implementation of a modem which transmits digital data on GSM voice channel. SIU 2015: 2537-2540 - [e3]Berna Örs, Bart Preneel
:
Cryptography and Information Security in the Balkans - First International Conference, BalkanCryptSec 2014, Istanbul, Turkey, October 16-17, 2014, Revised Selected Papers. Lecture Notes in Computer Science 9024, Springer 2015, ISBN 978-3-319-21355-2 [contents] - 2014
- [j7]Ahmet Dogan, Siddika Berna Örs
, Gökay Saldamli:
Analyzing and comparing the AES architectures for their power consumption. J. Intell. Manuf. 25(2): 263-271 (2014) - [c22]Ahmet Cagri Bagbaba
, Siddika Berna Örs
, Ahmet Turan Erozan:
Image filtering processor and its applications. SIU 2014: 2011-2014 - 2013
- [j6]Zaur Tariguliyev, Siddika Berna Örs Yalçin
:
Reliability and security of arbiter-based physical unclonable function circuits. Int. J. Commun. Syst. 26(6): 757-769 (2013) - [j5]Gildas Avoine, Muhammed Ali Bingöl
, Xavier Carpent
, Siddika Berna Örs Yalçin
:
Privacy-Friendly Authentication in RFID Systems: On Sublinear Protocols Based on Symmetric-Key Cryptography. IEEE Trans. Mob. Comput. 12(10): 2037-2049 (2013) - [c21]Abidin Altintas, Berna Örs
:
System level design of scalable encryption algorithm by using CoWare. CITS 2013: 1-4 - [c20]Subutay Giray Baskir, Siddika Berna Örs
:
Implementation of a secure RFID protocol. SIU 2013: 1-4 - [c19]Seyyid M. Dilek, Siddika Berna Örs Yalçin
, Mesut Kartal:
Reed-solomon decoder hardware implementation for DVB-S receiver. SIU 2013: 1-4 - [c18]Ahmet Turan Erozan, Subutay Giray Baskir, Siddika Berna Örs
:
Hardware/Software codesign for watermarking in DCT domain. SIU 2013: 1-4 - [c17]Okan Emre Ozen, Siddika Berna Örs Yalçin
, H. Bulent Yagci:
Design and implementation of a secure RFID system on FPGA. SIU 2013: 1-4 - 2011
- [c16]Ahmet Aris
, Siddika Berna Örs
, Gökay Saldamli:
Architectures for Fast Modular Multiplication. DSD 2011: 434-437 - [c15]Mehmet Soybali, Siddika Berna Örs
, Gökay Saldamli:
Implementation of a PUF Circuit on a FPGA. NTMS 2011: 1-5 - 2010
- [e2]Siddika Berna Örs Yalçin:
Radio Frequency Identification: Security and Privacy Issues - 6th International Workshop, RFIDSec 2010, Istanbul, Turkey, June 8-9, 2010, Revised Selected Papers. Lecture Notes in Computer Science 6370, Springer 2010, ISBN 978-3-642-16821-5 [contents]
2000 – 2009
- 2009
- [c14]Abid Uveys Danis, Berna Örs
:
Differential power analysis attack considering decoupling capacitance effect. ECCTD 2009: 359-362 - [e1]Atilla Elçi, Oleg B. Makarevich, Mehmet A. Orgun, Alexander G. Chefranov, Josef Pieprzyk, Yuri Anatolievich Bryukhomitsky, Siddika Berna Örs:
Proceedings of the 2nd International Conference on Security of Information and Networks, SIN 2009, Gazimagusa, North Cyprus, October 6-10, 2009. ACM 2009, ISBN 978-1-60558-412-6 [contents] - 2008
- [j4]Siddika Berna Örs
, Lejla Batina, Bart Preneel, Joos Vandewalle:
Hardware implementation of an elliptic curve processor over GF(p) with Montgomery modular multiplier. Int. J. Embed. Syst. 3(4): 229-240 (2008) - [c13]Ali Can Atici, Lejla Batina, Junfeng Fan, Ingrid Verbauwhede
, Siddika Berna Örs
:
Low-cost implementations of NTRU for pervasive security. ASAP 2008: 79-84 - [c12]Keklik Alptekin Bayam, Siddika Berna Örs
:
Differential Power Analysis resistant hardware implementation of the RSA cryptosystem. ISCAS 2008: 3314-3317 - [c11]Ilker Yavuz, Siddika Berna Örs Yalçin
, Çetin Kaya Koç:
FPGA Implementation of an Elliptic Curve Cryptosystem over GF(3^m). ReConFig 2008: 397-402 - 2007
- [j3]Elke De Mulder, Siddika Berna Örs
, Bart Preneel, Ingrid Verbauwhede
:
Differential power and electromagnetic attacks on a FPGA implementation of elliptic curve cryptosystems. Comput. Electr. Eng. 33(5-6): 367-382 (2007) - [c10]Levent Ordu, Siddika Berna Örs
:
Power Analysis Resistant Hardware Implementations of AES. ICECS 2007: 1408-1411 - 2004
- [j2]Nele Mentens, Siddika Berna Örs, Bart Preneel, Joos Vandewalle:
An FPGA Implementation of a Montgomery Multiplier Over GF(2^m). Comput. Artif. Intell. 23(5): 487-499 (2004) - [c9]François-Xavier Standaert
, Siddika Berna Örs
, Bart Preneel:
Power Analysis of an FPGA: Implementation of Rijndael: Is Pipelining a DPA Countermeasure? CHES 2004: 30-44 - [c8]Lejla Batina, Geeke Bruin-Muurling, Siddika Berna Örs
:
Flexible Hardware Design for RSA and Elliptic Curve Cryptosystems. CT-RSA 2004: 250-263 - [c7]François-Xavier Standaert
, Siddika Berna Örs
, Jean-Jacques Quisquater, Bart Preneel:
Power Analysis Attacks Against FPGA Implementations of the DES. FPL 2004: 84-94 - [c6]Nele Mentens, Siddika Berna Örs, Bart Preneel:
An FPGA implementation of an elliptic curve processor GF(2m). ACM Great Lakes Symposium on VLSI 2004: 454-457 - [c5]Siddika Berna Örs
, Frank K. Gürkaynak, Elisabeth Oswald, Bart Preneel:
Power-Analysis Attack on an ASIC AES implementation. ITCC (2) 2004: 546-552 - 2003
- [j1]Lejla Batina, Siddika Berna Örs
, Bart Preneel, Joos Vandewalle:
Hardware architectures for public key cryptography. Integr. 34(1-2): 1-64 (2003) - [c4]Siddika Berna Örs
, Lejla Batina, Bart Preneel, Joos Vandewalle:
Hardware Implementation of an Elliptic Curve Processor over GF(p). ASAP 2003: 433-443 - [c3]Siddika Berna Örs
, Elisabeth Oswald
, Bart Preneel:
Power-Analysis Attacks on an FPGA - First Experimental Results. CHES 2003: 35-50 - [c2]Siddika Berna Örs
, Lejla Batina, Bart Preneel, Joos Vandewalle:
Hardware Implementation of a Montgomery Modular Multiplier in a Systolic Array. IPDPS 2003: 184
1990 – 1999
- 1999
- [c1]Siddika Berna Örs
, Ahmet Dervisoglu:
Modeling Bit Multiplication Blocks for DSP Applications Using VHDL. EUROMICRO 1999: 1402-1405
Coauthor Index
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last updated on 2024-08-22 19:46 CEST by the dblp team
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