"Identifying a Subset of System Verilog Assertions for Efficient Bounded ..."

Robert Wille et al. (2008)

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DOI: 10.1109/DSD.2008.53

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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  - https://dblp.org/rec/conf/dsd/WilleFMALD08
Robert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler:
Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. DSD 2008: 542-549

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