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ORCIDDSD 2008: Parma, Italy
- Luca Fanucci:
11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008. IEEE Computer Society 2008, ISBN 978-0-7695-3277-6
Prospective Aspects of Networks-on-Chip
- Abdellah-Medjadji Kouadri-Mostefaoui, Benaoumeur Senouci, Frédéric Pétrot:
Large Scale On-Chip Networks : An Accurate Multi-FPGA Emulation Platform. 3-9 - Alberto Ferrante
, Simone Medardoni, Davide Bertozzi:
Network Interface Sharing Techniques for Area Optimized NoC Architectures. 10-17 - Dario Frazzetta, Giuseppe Dimartino, Maurizio Palesi, Shashi Kumar, Vincenzo Catania:
Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links. 18-25 - Rafael Tornero, Juan Manuel Orduña, Andres Mejia, José Flich, José Duato:
CART: Communication-Aware Routing Technique for Application-Specific NoCs. 26-31 - Sergio Saponara, Francesco Vitullo, Riccardo Locatelli, Philippe Teninge, Marcello Coppola, Luca Fanucci:
LIME: A Low-latency and Low-complexity On-chip Mesochronous Link with Integrated Flow Control. 32-35
NEWCOM++: Flexible Radio Digital Design
- Muhammad Najam-ul-Islam, Rizwan Rasheed, Renaud Pacalet, Raymond Knopp, Karim Khalfallah:
Flexible Baseband Architectures for Future Wireless Systems. 39-46 - Ismael Gómez, Vuk Marojevic, José Salazar, Antoni Gelonch:
A Lightweight Operating Environment for Next Generation Cognitive Radios. 47-52 - Ruimin Huang, Niklas Lotze, Yiannos Manoli:
On Design a High Speed Sigma Delta DAC Modulator for a Digital Communication Transceiver on Chip. 53-60 - Laurent Alaus, Dominique Noguet, Jacques Palicot:
A Reconfigurable LFSR for Tri-standard SDR Transceiver, Architecture and Complexity Analysis. 61-67
Fault Tolerance in Digital System Design - I
- Viacheslav Izosimov, Paul Pop, Petru Eles, Zebo Peng:
Synthesis of Flexible Fault-Tolerant Schedules with Preemption for Mixed Soft and Hard Real-Time Systems. 71-80 - Martin Straka, Zdenek Kotásek, Jan Winter:
Digital Systems Architectures Based on On-line Checkers. 81-87 - Cristiana Bolchini, Antonio Miele, Donatella Sciuto:
Fault Models and Injection Strategies in SystemC Specifications. 88-95 - Petr Fiser, Pavel Kubalík, Hana Kubátová:
An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA. 96-99 - Jirí Kvasnicka, Pavel Kubalík, Hana Kubátová:
Experimental SEU Impact on Digital Design Implemented in FPGAs. 100-103
System-Level Energy Optimization of Embedded Software
- Andrea Alimonda, Andrea Acquaviva, Salvatore Carta:
Temperature and Leakage Aware Power Control for Embedded Streaming Applications. 107-114 - Carlo Brandolese:
Source-Level Estimation of Energy Consumption and Execution Time of Embedded Software. 115-123 - Sébastien Bilavarn, Cécile Belleudy, Michel Auguin, T. Dupont, Anne-Marie Fouilliart:
Embedded Multicore Implementation of a H.264 Decoder with Power Management Considerations. 124-130
MPSOC and Interconnects
- Markus Winter, Gerhard P. Fettweis:
A Network-on-Chip Channel Allocator for Run-Time Task Scheduling in Multi-Processor System-on-Chips. 133-140 - Simone Secchi, Francesca Palumbo, Danilo Pani, Luigi Raffo:
A Network on Chip Architecture for Heterogeneous Traffic Support with Non-Exclusive Dual-Mode Switching. 141-148 - Magnus Själander, Andrei Sergeevich Terechko, Marc Duranton:
A Look-Ahead Task Management Unit for Embedded Multi-Core Architectures. 149-157 - Matteo Monchiero, Gianluca Palermo, Cristina Silvano, Oreste Villa:
A Modular Approach to Model Heterogeneous MPSoC at Cycle Level. 158-164 - Ali Jahanian, Morteza Saheb Zamani:
Performance and Timing Yield Enhancement using Highway-on-Chip Planning. 165-172 - Thomas Sødring, Åshild Grønstad Solheim, Tor Skeie, Sven-Arne Reinemo:
An Analysis of Connectivity and Yield for 2D Mesh Based NoC with Interconnect Router Failures. 173-178
Video and Image Processing
- Nuno Sebastião, Tiago Dias, Nuno Roma, Paulo F. Flores, Leonel Sousa:
Application Specific Programmable IP Core for Motion Estimation: Technology Comparison Targeting Efficient Embedded Co-Processing Units. 181-188 - Roberto Giorgi, Zdravko Popovic, Nikola Puzovic, Arnaldo Azevedo, Ben H. H. Juurlink:
Analyzing Scalability of Deblocking Filter of H.264 via TLP Exploitation in a New Many-Core Architecture. 189-194 - Theja Tulabandhula, Amit Patra, Nirmal B. Chakrabarti:
Design of a Two Dimensional PRSI Image Processor. 195-202 - Vasily G. Moshnyaga, Koji Hashimoto, Tadashi Suetsugu:
A Hardware Design for Camera-Based Power Management of Computer Monitor. 203-209 - Roderick R. Colenbrander, Arjen S. Damstra, C. Wim Korevaar, C. A. Verhaar, Albert Molderink:
Co-design and Implementation of the H.264/AVC Motion Estimation Algorithm Using Co-simulation. 210-215
Fault Tolerance in Digital System Design - II
- Demid Borodin, Ben H. H. Juurlink:
A Low-Cost Cache Coherence Verification Method for Snooping Systems. 219-227 - Radek Dobias, Jan Konarski, Hana Kubátová:
Dependability Evaluation of Real Railway Interlocking Device. 228-233 - Toshimasa Funaki, Toshinori Sato:
Formulating MITF for a Multicore Processor with SEU Tolerance. 234-241 - Gottfried Fuchs, Matthias Függer, Ulrich Schmid, Andreas Steininger:
Mapping a Fault-Tolerant Distributed Algorithm to Systems on Chip. 242-249 - Andrzej Krasniewski:
Concurrent Error Detection for a Network of Combinational Logic Blocks Implemented with Memory Embedded in FPGAs. 250-255
Power Issues
- Andrea Marongiu, Luca Benini, Andrea Acquaviva, Andrea Bartolini:
Analysis of Power Management Strategies for a Large-Scale SoC Platform in 65nm Technology. 259-266 - Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Esther Andres Perez, Román Hermida:
Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis. 267-273 - Behnam Ghavami, Mehrshad Khosraviani, Hossein Pedram:
Power Optimization of Asynchronous Circuits through Simultaneous Vdd and Vth Assignment and Template Sizing. 274-281 - Sudip Roy, Ajit Pal:
Why to Use Dual-Vt, If Single-Vt Serves the Purpose Better under Process Parameter Variations? 282-289 - Sharareh Zamanzadeh, Mohammad Mirza-Aghatabar, Mehrdad Najibi, Hossein Pedram, Abolghasem Sadeghi:
Reimbursing the Handshake Overhead of Asynchronous Circuits using Compiler Pre-Synthesis Optimizations. 290-297 - Enrico Macii, Letícia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Massimo Poncino:
Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. 298-303
Design, Modeling and Verification of Cache and Cache-based Systems
- Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete, Per Stenström:
Leveraging Data Promotion for Low Power D-NUCA Caches. 307-316 - Zhen Liu, Jia Yu, Xiaojun Wang, Bin Liu, Laxmi N. Bhuyan:
Revisiting the Cache Effect on Multicore Multithreaded Network Processors. 317-324 - Ahmed Abdallah, Wayne H. Wolf, Graham R. Hellestrand:
Using Empirical Science to Engineer Systems: Optimizing Cache for Power and Performance. 325-333 - Roberto Giorgi, Paolo Bennati:
Reducing Leakage through Filter Cache. 334-341
FPGA and Reconfigurable Architectures - I
- Christophe Wolinski, Krzysztof Kuchcinski, Jürgen Teich, Frank Hannig:
Communication Network Reconfiguration Overhead Optimization in Programmable Processor Array Architectures. 345-352 - Sergio Saponara, Nicola E. L'Insalata, Tony Bacchillone, Esa Petri, Iacopo Del Corona, Luca Fanucci:
Hardware/Software FPGA-based Network Emulator for High-speed On-board Communications. 353-359 - Alessandro Cilardo, Nicola Mazzocca, Luigi Coppolino:
Virtual Scan Chains for Online Testing of FPGA-based Embedded Systems. 360-366 - Tommaso Cecchini, Francesco Sechi, Luca Bacciarelli, Luca Mostardini, Francesco Battini, Luca Fanucci, Marco De Marinis:
Pin-limited Frequency Downscaler AHB Bridge for ASIC to FPGA Communication. 367-372 - Maurizio Tranchero, Leonardo Maria Reyneri:
Implementation of Self-Timed Circuits onto FPGAs Using Commercial Tools. 373-380
Applications of Digital Systems
- Huiju Cheng, Howard M. Heys, Cheng Wang:
PUFFIN: A Novel Compact Block Cipher Targeted to Embedded Digital Systems. 383-390 - Rainer Schaffer, Renate Merker, Frank Hannig, Jürgen Teich:
Utilization of all Levels of Parallelism in a Processor Array with Subword Parallelism. 391-398 - Paola Baldrighi, Marco Castellano, Carla Vacchi, Davide Canina, Paolo Golzi, Gianni Ferrante:
Digital Nuclear Magnetic Resonance Acquisition Channel. 399-404 - Gianmaria Collazuol, S. Galeotti, E. Imbergamo, G. Lamanna, Guido Magazzù, M. Sozzi:
Fast FPGA-based Trigger and Data Acquisition System for the CERN Experiment NA62: Architecture and Algorithms. 405-412 - Luca Bassi, Enrico Boni, Andrea Cellai, Alessandro Dallai, Francesco Guidi, Stefano Ricci, Piero Tortoli:
A Novel Digital Ultrasound System for Experimental Research Activities. 413-417 - François Charot, Christophe Wolinski, Nicolas Fau, François Hamon:
A Parallel and Modular Architecture for 802.16e LDPC Codes. 418-421 - Stefano Recchi, Maurizio Persichitti, Massimo Conti:
WirelessUSB - Performance Analysis of an Embedded System in a Peer-to-Peer Application. 422-426 - Francesco Sechi, Luca Fanucci, Stefano Luschi, Simone Perini, Matteo Madesani:
Design of a Distributed Embedded System for Domotic Applications. 427-431 - Giovanni Danese, Mauro Giachero, Francesco Leporati, Nelson Nazzicari, M. Nobis:
An Embedded Acquisition System for Remote Monitoring of Tire Status in F1 Race Cars through Thermal Images. 432-437 - Gianni Antichi, Andrea Di Pietro, Domenico Ficara, Stefano Giordano, Gregorio Procissi, Fabio Vitucci:
Design of a High Performance Traffic Generator on Network Processor. 438-441 - Paola Baldrighi, Marco Maurizio Maggi, Marco Castellano, Carla Vacchi, Davide Crespi, Piero Bonifacino:
Implementation of Microprogrammed Hard Disk Drive Servo Sequencer. 442-446 - Blaz Lampreht, Luka Stepancic, Igor Vizec, Bostjan Zankar, Miha Mraz, Iztok Lebar Bajec, Primoz Pecar:
Quantum-Dot Cellular Automata Serial Comparator. 447-452
Synthesis
- José Luis Risco-Martín, David Atienza, José Ignacio Hidalgo, Juan Lanchares:
Design Flow of Dynamically-Allocated Data Types in Embedded Applications Based on Elitist Evolutionary Computation Optimization. 455-463 - Pedro Garcia-Repetto, María C. Molina, Rafael Ruiz-Sautua, Guillermo Botella Juan:
Exploiting Internal Operation Patterns during the High-Level Synthesis of Time-Constrained Circuits. 464-471 - Minoo Mirsaeedi, Morteza Saheb Zamani, Mehdi Saeedi:
Multi-Objective Statistical Yield Enhancement using Evolutionary Algorithm. 472-479 - Lech Józwiak, Szymon Bieganski:
Technology Library Modelling for Information-driven Circuit Synthesis. 480-489 - Mehdi Saeedi, Naser MohammadZadeh, Mehdi Sedighi, Morteza Saheb Zamani:
Evaluation and Improvement of Quantum Synthesis Algorithms based on a Thorough Set of Metrics. 490-493 - George Economakos, Sotirios Xydis:
A Scheduling Postprocessor to Exploit Morphable RTL Components During High-Level Synthesis. 494-499
Planning and Optimization of Sensor Network Systems - I
- Itziar Marín, Aitzol Zuloaga, Iker Losada:
A Novel Technique for Low Latency Data Gathering in Wireless Sensor Networks. 503-511 - Michele Magno, Davide Brunelli, Piero Zappi, Luca Benini:
A Solar-powered Video Sensor Node for Energy Efficient Multimodal Surveillance. 512-519 - Roberto Alesii, Fabio Graziosi, Luigi Pomante, Claudia Rinaldi:
Exploiting WSN for Audio Surveillance Applications: The VoWSN Approach. 520-524 - Marcello Mura, Mariagiovanna Sami:
Code Generation from Statecharts: Simulation of Wireless Sensor Networks. 525-532
Hardware Checking
- Tsau-Shuan Wu, Alkan Cengiz, Tom W. Chen:
Improving SER Immunity of Combinational Logic Using Combinations of Spatial and Temporal Checking. 535-541 - Robert Wille, Görschwin Fey, Marc Messing, Gerhard Angst, Lothar Linhard, Rolf Drechsler:
Identifying a Subset of System Verilog Assertions for Efficient Bounded Model Checking. 542-549 - Giacomo Paci, Axel Nackaerts, Francky Catthoor, Luca Benini, Paul Marchal:
How to Live with Uncertainties: Exploiting the Performance Benefits of Self-Timed Logic In Synchronous Design. 550-557 - Morteza Saheb Zamani, Maryam Taajobian, Mehdi Saeedi:
An Efficient Non-Tree Clock Routing Algorithm for Reducing Delay Uncertainty. 558-565 - A. Neslin Ismailoglu, Murat Askar:
SDIVA: Structural Delay Insensitivity Verification Analysis Method for Bit-Level Pipelined Systolic Arrays with Early Output Evaluation. 566-571
FPGA and Reconfigurable Architectures - II
- Scott Miller, Ambrose Chu, Mihai Sima, Michael McGuire:
VLSI Implementation of a Cryptography-Oriented Reconfigurable Array. 575-583 - Yoonjin Kim, Rabi N. Mahapatra:
A New Array Fabric for Coarse-Grained Reconfigurable Architecture. 584-591 - Izhar Zaidi, Atukem Nabina, Cedric Nishan Canagarajah, José L. Núñez-Yáñez:
Power/Area Analysis of a FPGA-Based Open-Source Processor using Partial Dynamic Reconfiguration. 592-598 - Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsch:
System-on-an-FPGA Design for Real-time Particle Track Recognition and Reconstruction in Physics Experiments. 599-605
Design Methodologies
- Jan W. M. Jacobs, Leroy van Engelen, Jan Kuper, Gerard J. M. Smit, Rui Dai:
IRIS: A Firmware Design Methodology for SIMD Architectures. 609-617 - Carlo Brandolese, William Fornaciari:
Measurement, Analysis and Modeling of RTOS System Calls Timing. 618-625 - Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas:
Development of Functional Delay Tests. 626-632 - Muhammad Rashid, Damien Picard, Bernard Pottier:
Application Analysis for Parallel Processing. 633-640 - Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria:
Discrete Particle Swarm Optimization for Multi-objective Design Space Exploration. 641-644 - Martino Ruggiero, Michele Lombardi, Michela Milano, Luca Benini:
Cellflow: A Parallel Application Development Environment with Run-Time Support for the Cell BE Processor. 645-650 - Sebastien Fontaine, Luc Filion, Guy Bois:
Exploring ISS Abstractions for Embedded Software Design. 651-655 - Vincenzo Catania, Gianmarco De Francisci Morales, Alessandro G. Di Nuovo, Maurizio Palesi, Davide Patti:
High Performance Computing for Embedded System Design: A Case Study. 656-659 - Joseph C. Libby, Farnaz Gharibian, Kenneth B. Kent:
Automatic Identification of Parallelism in Handel-C. 660-664 - Takashi Kambe, Makoto Saituji:
A Variable Length Vector Pipeline Architecture Design Methodology. 665-668
Planning and Optimization of Sensor Network Systems - II
- R. Morales-Ramos, Alexander Vaz, Daniel Pardo, Roc Berenguer:
Ultra-Low Power Passive UHF RFID for Wireless Sensor Networks. 671-675 - Simone Campanoni, William Fornaciari:
Models and Tradeoffs in WSN System-Level Design. 676-684 - Stefano Tennina, Marco Di Renzo, Fabio Graziosi, Fortunato Santucci:
Pearson - based Analysis of Positioning Error Distribution in Wireless Sensor Networks. 685-692 - Abdalkarim Awad, Rodrigo Nebel, Reinhard German, Falko Dressler:
On the Need for Passive Monitoring in Sensor Networks. 693-699
Dependability and Testing of Digital Systems - I
- Jiri Jenícek:
Efficient Test Pattern Compression Method Using Hard Fault Preferring. 703-708 - Christophe Le Blanc, Éric Colinet, Jérôme Juillard, Lorena Anghel:
Digital Implementation of a BIST Method based on Binary Observations. 709-713 - Mohammad Reza Kakoee, Mohammad Riazati, Siamak Mohammadi:
Generating RTL Synthesizable Code from Behavioral Testbenches for Hardware-Accelerated Verification. 714-720 - Jaroslav Skarvada, Zdenek Kotásek, Tomas Herrman:
Power Conscious RTL Test Scheduling. 721-728 - Witold A. Pleskacz, Maksim Jenihhin, Jaan Raik, Michal Rakowski, Raimund Ubar, Wieslaw Kuzmicz:
Hierarchical Analysis of Short Defects between Metal Lines in CMOS IC. 729-734 - Primoz Puhar, Andrej Zemva:
Functional Verification of a USB Host Controller. 735-740
Digital Signal Processing - I
- Silvia Franchini, Antonio Gentile, Filippo Sorbello, Giorgio Vassallo, Salvatore Vitabile:
An FPGA Implementation of a Quadruple-Based Multiplier for 4D Clifford Algebra. 743-751 - Haridimos T. Vergos, Dimitris Bakalis:
On the Use of Diminished-1 Adders for Weighted Modulo 2n + 1 Arithmetic Components. 752-759 - Daniel Piso Fernandez, Javier D. Bruguera:
A New Rounding Algorithm for Variable Latency Division and Square Root Implementations. 760-767 - Pedro Miguens Matutino, Leonel Sousa:
An RNS based Specific Processor for Computing the Minimum Sum-of-Absolute-Differences. 768-775
System Synthesis
- Enrique San Millán, Luis Entrena, José Alberto Espejo:
Logic Transformations by Multiple Wire Network Addition. 779-786 - Anna Bernasconi, Valentina Ciriani, Roberto Cordone:
On Projecting Sums of Products. 787-794 - Petr Mikusek, Vaclav Dvorak:
On Lookup Table Cascade-Based Realizations of Arbiters. 795-802 - Ehsan K. Ardestani, Morteza Saheb Zamani, Mehdi Sedighi:
A Fast Transformation-Based Synthesis Algorithm for Reversible Circuits. 803-806
Wireless Systems
- Valentina Bianchi, Ferdinando Grossi, Guido Matrella, Ilaria De Munari, Paolo Ciampolini:
A Wireless Sensor Platform for Assistive Technology Applications. 809-816 - Pawel Gburzynski, Bozena Kaminska, Ashikur Rahman:
Reliable Data Transmission over Simple Wireless Channels: A Case Study. 817-824 - Ding G. Guo, Francis Eng Hock Tay, Lin Xu, L. M. Yu, Myo Naing Nyan, F. W. Chong, K. L. Yap, B. Xu:
A Long-term Wearable Vital Signs Monitoring System using BSN. 825-830 - Andrea Ricci, Matteo Grisanti, Ilaria De Munari, Paolo Ciampolini:
Design of an Ultra Low-Power RFID Baseband Processor Featuring an AES Cryptography Engine. 831-838 - Alessandro Mignogna, Massimo Conti, M. D'Angelo, Massimo Baleani, Alberto Ferrari:
Transaction Level Modeling and Performance Analysis in SystemC of IEEE 802.15.4 Wireless Standard. 839-843 - Goran Panic, Daniel Dietterle, Zoran Stamenkovic:
Architecture of a Power-Gated Wireless Sensor Node. 844-849 - Paris Kitsos, George N. Selimis, Odysseas G. Koufopavlou, Athanassios N. Skodras:
A Hardware Implementation of CURUPIRA Block Cipher for Wireless Sensors. 850-853
Dependability and Testing of Digital Systems - II
- Morteza Damavandpeyma, Siamak Mohammadi:
Architectural Synthesis with Control Data Flow Extraction toward an Asynchronous CAD Tool. 857-864 - Josef Strnadel:
TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path. 865-872 - Heinrich Theodor Vierhaus, René Kothe:
Embedded Diagnostic Logic Test Exploiting Regularity. 873-879 - Tsutomu Sasao, Yukihiro Iguchi:
On the Complexity of Error Detection Functions for Redundant Residue Number Systems. 880-887
Digital Signal Processing - II
- Shinobu Nagayama, Jon T. Butler, Tsutomu Sasao:
Programmable Numerical Function Generators for Two-Variable Functions. 891-898 - Francisco J. Jaime, Javier Hormigo, Julio Villalba, Emilio L. Zapata:
SIMD Enhancements for a Hough Transform Implementation. 899-903 - Shahid Mehmood, Stefano Cagnoni, Monica Mordonini, Guido Matrella:
Hardware-oriented Adaptation of a Particle Swarm Optimization Algorithm for Object Detection. 904-911
Parallel Architectures
- Zubair Nawaz, Zaid Al-Ars, Koen Bertels, Mudassir Shabbir:
Acceleration of Smith-Waterman using Recursive Variable Expansion. 915-922 - Shruti Patil, Venkatesan Muthukumar:
Maximizing Resource Utilization by Slicing of Superscalar Architecture. 923-930
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