"A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs."

Vamsi Boppana et al. (1996)

> Home

Details and statistics

DOI: 10.1007/3-540-61626-8_109

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-22

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - conf/europar/BoppanaSBFL96
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/europar/BoppanaSBFL96
Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu:
A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. Euro-Par, Vol. I 1996: 828-831

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.