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2010 – 2019
- 2019
[c31]Sagheer Ahmad, Sridhar Subramanian, Vamsi Boppana, Shankar Lakka, Fu-Hing Ho, Tomai Knopp, Juanjo Noguera, Gaurav Singh, Ralph Wittig:
Xilinx First 7nm Device: Versal AI Core (VC1902). Hot Chips Symposium 2019: 1-28- 2016
- [j4]Sagheer Ahmad, Vamsi Boppana, Ilya Ganusov, Vinod Kathail, Vidya Rajagopalan, Ralph Wittig:
A 16-nm Multiprocessing System-on-Chip Field-Programmable Gate Array Platform. IEEE Micro 36(2): 48-62 (2016) - 2015
- [c30]Vamsi Boppana, Sagheer Ahmad, Ilya Ganusov, Vinod Kathail, Vidya Rajagopalan, Ralph Wittig:
UltraScale+ MPSoC and FPGA families. Hot Chips Symposium 2015: 1-37 - 2011
- [c29]Vidya Rajagopalan, Vamsi Boppana, Sandeep Dutta, Brad Taylor, Ralph Wittig:
Xilinx Zynq-7000 EPP: An extensible processing platform family. Hot Chips Symposium 2011: 1-24
2000 – 2009
- 2008
- [c28]Shashank Bhonge, Vamsi Boppana:
Low power chips: a fabless asic perspective. ISLPED 2008: 347-348 - [c27]Vamsi Boppana, Rahoul Varma, S. Balajee:
Implementing the Best Processor Cores. VLSI Design 2008: 17-18 - 2005
- [j3]Rob Roy, Debashis Bhattacharya, Vamsi Boppana:
Transistor-Level Optimization of Digital Designs with Flex Cells. Computer 38(2): 53-61 (2005) - 2004
- [c26]Hiroaki Yoshida, Kaushik De, Vamsi Boppana:
Accurate pre-layout estimation of standard cell characteristics. DAC 2004: 208-211 - 2003
- [j2]M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana:
Fault equivalence identification in combinational circuits using implication and evaluation techniques. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(7): 922-936 (2003) - 2002
- [c25]Indradeep Ghosh
, Krishna Sekar, Vamsi Boppana:
Design for Verification at the Register Transfer Level. ASP-DAC/VLSI Design 2002: 420-425 - 2001
- [j1]Srivaths Ravi, Indradeep Ghosh, Vamsi Boppana, Niraj K. Jha:
Fault-diagnosis-based technique for establishing RTL and gate-levelcorrespondences. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(12): 1414-1425 (2001) - [c24]Biplab K. Sikdar, Debesh K. Das, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee, Parimal Pal Chaudhuri:
Cellular automata as a built in self test structure. ASP-DAC 2001: 319-324 - [c23]M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana:
Fault Equivalence Identification Using Redundancy Information and Static and Dynamic Extraction. VTS 2001: 124-130 - 2000
- [c22]Srivaths Ravi, Niraj K. Jha, Indradeep Ghosh, Vamsi Boppana:
A Technique for Identifying RTL and Gate-Level Correspondences. ICCD 2000: 591-594 - [c21]Vamsi Boppana, Indradeep Ghosh, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita:
Hierarchical Error Diagnosis Targeting RTL Circuits. VLSI Design 2000: 436-441 - [c20]Biplab K. Sikdar, Kolin Paul, Gosta Pada Biswas, Parimal Pal Chaudhuri, Vamsi Boppana, Cliff Yang, Sobhan Mukherjee:
Theory and Application of GF(2p) Cellular Automata as On-chip Test Pattern Generator. VLSI Design 2000: 556-561 - [c19]Ankur Jain, Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Michael S. Hsiao:
Testing, Verification, and Diagnosis in the Presence of Unknowns. VTS 2000: 263-270
1990 – 1999
- 1999
- [c18]Vamsi Boppana, Sreeranga P. Rajan, Koichiro Takayama, Masahiro Fujita:
Model Checking Based on Sequential ATPG. CAV 1999: 418-430 - [c17]Vamsi Boppana, Rajarshi Mukherjee, Jawahar Jain, Masahiro Fujita, Pradeep Bollineni:
Multiple Error Diagnosis Based on Xlists. DAC 1999: 660-665 - [c16]M. Enamul Amyeen, W. Kent Fuchs, Irith Pomeranz, Vamsi Boppana:
Implication and Evaluation Techniques for Proving Fault Equivalence. VTS 1999: 201-213 - [c15]Ankur Jain, Michael S. Hsiao, Vamsi Boppana, Masahiro Fujita:
On the Evaluation of Arbitrary Defect Coverage of Test Sets. VTS 1999: 426-432 - 1998
- [c14]Vamsi Boppana, W. Kent Fuchs:
Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits. ICCAD 1998: 147-154 - [c13]Vamsi Boppana, Masahiro Fujita:
Modeling the unknown! Towards model-independent fault and error diagnosis. ITC 1998: 1094-1101 - 1997
- [b1]Vamsi Boppana:
State Information-Based Solutions for Sequential Circuit Diagnosis and Testing. University of Illinois Urbana-Champaign, USA, 1997 - [c12]Vamsi Boppana, Ismed Hartanto, W. Kent Fuchs:
Characterization and Implicit Identification of Sequential Indistinguishability. VLSI Design 1997: 376-380 - [c11]Ismed Hartanto, Vamsi Boppana, Janak H. Patel, W. Kent Fuchs:
Diagnostic Test Pattern Generation for Sequential Circuits. VTS 1997: 196-202 - 1996
- [c10]Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu:
A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. Euro-Par, Vol. I 1996: 828-831 - [c9]Vamsi Boppana, Ismed Hartanto, W. Kent Fuchs:
Fault Diagnosis Using State Information. FTCS 1996: 96-103 - [c8]Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs:
Identification of unsettable flip-flops for partial scan and faster ATPG. ICCAD 1996: 63-66 - [c7]Vamsi Boppana, W. Kent Fuchs:
Integrated fault diagnosis targeting reduced simulation. ICCAD 1996: 681-684 - [c6]Ismed Hartanto, Vamsi Boppana, W. Kent Fuchs:
Diagnostic Fault Equivalence Identification Using Redundancy Information and Structural Analysis. ITC 1996: 294-302 - [c5]Vamsi Boppana, W. Kent Fuchs:
Partial Scan Design Based on State Transition Modeling. ITC 1996: 538-547 - [c4]Vamsi Boppana, Ismed Hartanto, W. Kent Fuchs:
Full fault dictionary storage based on labeled tree encoding. VTS 1996: 174-179 - 1994
- [c3]Vamsi Boppana, W. Kent Fuchs:
Fault dictionary compaction by output sequence removal. ICCAD 1994: 576-579 - [c2]Sukumar Nandi, Vamsi Boppana, Parimal Pal Chaudhuri:
A CAD Tool for Design of On-Chip Store & Generate Scheme. VLSI Design 1994: 169-174 - 1993
- [c1]Sukumar Nandi, Vamsi Boppana, Supratik Chakraborty, Parimal Pal Chaudhuri, Samir Roy:
Delay Fault Test Generation with Cellular Automata. VLSI Design 1993: 281-286
Coauthor Index
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