"A low power and low cost scan test architecture for multi-clock domain ..."

Arasu T. Senthil, C. P. Ravikumar, Soumitra Kumar Nandy (2005)

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DOI: 10.1109/TEST.2005.1583995

access: closed

type: Conference or Workshop Paper

metadata version: 2023-03-23

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Arasu T. Senthil, C. P. Ravikumar, Soumitra Kumar Nandy:
A low power and low cost scan test architecture for multi-clock domain SoCs using virtual divide and conquer. ITC 2005: 9

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