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2020 – today
- 2024
[c74]C. P. Ravikumar, N. Sasikala:
Predictive Modeling for Engineering Student Performance Forecasting and Course Correction. TALE 2024: 1-6- 2020
- [c73]C. P. Ravikumar:
Industrial Practices in Low-Power Robust Design. IOLTS 2020: 1-4
2010 – 2019
- 2018
- [j40]Ananya Ravikumar, C. P. Ravikumar:
Architectural Optimization of Hierarchically Organized Wireless Sensor Networks for Energy, Cost, and Security. J. Low Power Electron. 14(1): 8-17 (2018) - 2016
- [j39]C. P. Ravikumar:
Smart and Fault-Tolerant LED-Based Street Lamps. J. Low Power Electron. 12(3): 259-266 (2016) - 2013
- [i1]Namita Sharma, Vineet Sahula, C. P. Ravikumar:
Energy Aware Task Scheduling for Soft Real Time Systems using an Analytical Approach for Energy Estimation. CoRR abs/1303.0725 (2013) - 2012
- [j38]T. S. Rajesh Kumar, R. Govindarajan, C. P. Ravikumar:
On-chip memory architecture exploration framework for DSP processor-based embedded system on chip. ACM Trans. Embed. Comput. Syst. 11(1): 5:1-5:25 (2012)
2000 – 2009
- 2008
- [j37]V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti:
A Novel Power-Managed Scan Architecture for Test Power and Test Time Reduction. J. Low Power Electron. 4(1): 101-110 (2008) - [j36]C. P. Ravikumar, Mokhtar Hirech, Xiaoqing Wen:
Test Strategies for Low-Power Devices. J. Low Power Electron. 4(2): 127-138 (2008) - [c72]C. P. Ravikumar, Mokhtar Hirech, Xiaoqing Wen:
Test Strategies for Low Power Devices. DATE 2008: 728-733 - [c71]Aman Kokrady, C. P. Ravikumar, Nitin Chandrachoodan
:
Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models. VLSI Design 2008: 169-174 - [c70]T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan:
Memory Architecture Exploration Framework for Cache Based Embedded SOC. VLSI Design 2008: 553-559 - [e1]Vijaykrishnan Narayanan, C. P. Ravikumar, Jörg Henkel, Ali Keshavarzi, Vojin G. Oklobdzija, Barry M. Pangrle:
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008, Bangalore, India, August 11-13, 2008. ACM 2008, ISBN 978-1-60558-109-5 [contents] - 2007
- [j35]C. P. Ravikumar, Jari Nurmi:
Conference Reports. IEEE Des. Test Comput. 24(2): 202-203 (2007) - [j34]V. R. Devanathan, C. P. Ravikumar, V. Kamakoti:
Variation-Tolerant, Power-Safe Pattern Generation. IEEE Des. Test Comput. 24(4): 374-384 (2007) - [j33]Arasu T. Senthil, C. P. Ravikumar, S. K. Nandy:
Low-Power Hierarchical Scan Test for Multiple Clock Domains. J. Low Power Electron. 3(1): 106-118 (2007) - [j32]Nisar Ahmed, Mohammad Tehranipoor, C. P. Ravikumar, Kenneth M. Butler:
Local At-Speed Scan Enable Generation for Transition Fault Testing Using Low-Cost Testers. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(5): 896-906 (2007) - [j31]Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar:
A critical-path-aware partial gating approach for test power reduction. ACM Trans. Design Autom. Electr. Syst. 12(2): 17 (2007) - [c69]T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan:
MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip. ASP-DAC 2007: 492-497 - [c68]Yasuharu Kohiyama, C. P. Ravikumar, Yasuo Sato, Laung-Terng Wang, Yervant Zorian:
Next Generation Test, Diagnostics and Yield Challenges for EDA, ATE, IP and Fab - A Perspective from All Sides. ATS 2007: 207 - [c67]V. R. Devanathan, C. P. Ravikumar, V. Kamakoti:
Interactive presentation: On power-profiling and pattern generation for power-safe scan tests. DATE 2007: 534-539 - [c66]V. R. Devanathan, C. P. Ravikumar, V. Kamakoti:
A stochastic pattern generation and optimization framework for variation-tolerant, power-safe scan test. ITC 2007: 1-10 - [c65]V. R. Devanathan, C. P. Ravikumar, Rajat Mehrotra, V. Kamakoti:
PMScan : A power-managed scan for simultaneous reduction of dynamic and leakage power during scan test. ITC 2007: 1-9 - [c64]V. R. Devanathan, C. P. Ravikumar, V. Kamakoti:
Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms. VLSI Design 2007: 351-356 - [c63]T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan:
MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip. VLSI Design 2007: 527-533 - [c62]V. R. Devanathan, C. P. Ravikumar, V. Kamakoti:
Glitch-Aware Pattern Generation and Optimization Framework for Power-Safe Scan Test. VTS 2007: 167-172 - 2006
- [j30]Subhasish Mitra, Ondrej Novák, Hana Kubátová, Bashir M. Al-Hashimi, Erik Jan Marinissen, C. P. Ravikumar:
Conference Reports. IEEE Des. Test Comput. 23(4): 262-265 (2006) - [j29]V. R. Devanathan, C. P. Ravikumar, V. Kamakoti:
On Reducing Peak Capture Power of Transition Delay Fault Test for SoCs with Unwrapped Cores. J. Low Power Electron. 2(3): 464-476 (2006) - 2005
- [c61]Mohammed ElShoukry, Mohammad Tehranipoor, C. P. Ravikumar:
Partial Gating Optimization for Power Reduction During Test Application. Asian Test Symposium 2005: 242-247 - [c60]Arasu T. Senthil, C. P. Ravikumar, Soumitra Kumar Nandy:
A low power and low cost scan test architecture for multi-clock domain SoCs using virtual divide and conquer. ITC 2005: 9 - [c59]Nisar Ahmed, Mohammad Tehranipoor, C. P. Ravikumar:
Enhanced launch-off-capture transition fault testing. ITC 2005: 10 - [c58]C. P. Ravikumar, R. Dandamudi, V. R. Devanathan, N. Haldar, K. Kiran, P. S. Vijay Kumar:
A Framework for Distributed and Hierarchical Design-for-Test. VLSI Design 2005: 497-503 - [c57]Nisar Ahmed, C. P. Ravikumar, Mohammad Tehranipoor, Jim Plusquellic:
At-Speed Transition Fault Testing With Low Speed Scan Enable. VTS 2005: 42-47 - 2004
- [j28]Mohammed Fadle Abdulla, C. P. Ravikumar:
A self-checking signature scheme for checking backdoor security attacks in Internet. J. High Speed Networks 13(4): 309-317 (2004) - [c56]C. P. Ravikumar, Graham Hetherington:
A Holistic Parallel and Hierarchical Approach towards Design-For-Test. ITC 2004: 345-354 - [c55]C. P. Ravikumar:
Multiprocessor Architectures for Embedded System-on-chip Applications. VLSI Design 2004: 512-519 - [c54]Aman Kokrady, C. P. Ravikumar:
Fast, Layout-Aware Validation of Test-Vectors for Nanometer-Related Timing Failures. VLSI Design 2004: 597- - 2003
- [c53]Aman Kokrady, C. P. Ravikumar:
Static Verification of Test Vectors for IR Drop Failure. ICCAD 2003: 760-764 - [c52]C. P. Ravikumar, Nitin Kakkar, Saurabh Chopra:
Mutual Testing based on Wavelet Transforms. VLSI Design 2003: 347-352 - [c51]T. S. Rajesh Kumar, R. Govindarajan, C. P. Ravikumar:
Optimal Code and Data Layout in Embedded Systems. VLSI Design 2003: 573-578 - 2002
- [c50]Mirza Mohd. Sufyan Beg, C. P. Ravikumar:
Measuring the Quality of Web Search Results. JCIS 2002: 324-328 - [c49]Rahul Kumar, C. P. Ravikumar:
Leakage Power Estimation for Deep Submicron Circuits in an ASIC Design Environment. ASP-DAC/VLSI Design 2002: 45-50 - [c48]Vineet Sahula, C. P. Ravikumar, D. Nagchoudhuri:
Improvement of ASIC Design Processes. ASP-DAC/VLSI Design 2002: 105- - [c47]Shampa Chakraverty, C. P. Ravikumar, D. Roy Choudhuri:
An Evolutionary Scheme for Cosynthesis of Real-Time Systems. ASP-DAC/VLSI Design 2002: 251- - [c46]C. P. Ravikumar, Rahul Kumar:
Divide-and-Conquer IDDQ Testing for Core-Based System Chips. ASP-DAC/VLSI Design 2002: 761-766 - 2001
- [j27]C. P. Ravikumar, Vikas Jain, Anurag Dod:
Distributed Fault Simulation Algorithms on Parallel Virtual Machine. VLSI Design 12(1): 81-99 (2001) - [c45]Vineet Sahula, C. P. Ravikumar:
The Hierarchical Concurrent Flow Graph Approach for Modeling and Analysis of Design Processes. VLSI Design 2001: 91-96 - [c44]Vishal Dalal, C. P. Ravikumar:
Software Power Optimizations In An Embedded System. VLSI Design 2001: 254- - [c43]V. Sankara Subramanian, C. P. Ravikumar:
Estimating Crosstalk From Vlsi Layouts. VLSI Design 2001: 531- - 2000
- [j26]Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar:
A scheme for multiple on-chip signature checking for embedded SRAMS. J. Syst. Archit. 46(2): 181-199 (2000) - [c42]Rajesh Kannah, C. P. Ravikumar:
Functional Testing of Microprocessors with Graded Fault Coverage. Asian Test Symposium 2000: 204- - [c41]Shampa Chakraverty, C. P. Ravikumar:
A Stochastic Framework for Co-synthesis of Real-Time Systems. LCTES 2000: 96-113 - [c40]Anil Sharma, C. P. Ravikumar:
Efficient Implementation of ADPCM Codec. VLSI Design 2000: 456-461 - [c39]C. P. Ravikumar, Gaurav Chandra, Ashutosh Verma:
Simultaneous Module Selection and Scheduling for Power-Constrained Testing of Core Based Systems. VLSI Design 2000: 462-467
1990 – 1999
- 1999
- [j25]Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar:
Built-in Self Test Based on Multiple On-Chip Signature Checking. J. Electron. Test. 14(3): 227-244 (1999) - [j24]C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal:
A functional-level testability measure for register-level circuits and its estimation. Microprocess. Microsystems 22(9): 535-542 (1999) - [j23]C. P. Ravikumar:
High-Performance Cluster Computing. Volume 1: Architecutes and Systems. Volume 2: Programming and Applications. Parallel Distributed Comput. Pract. 2(4) (1999) - [c38]C. P. Ravikumar, Ashutosh Verma, Gaurav Chandra:
A Polynomial-Time Algorithm for Power Constrained Testing of Core Based Systems. Asian Test Symposium 1999: 107-112 - [c37]Rohit Sharma, C. P. Ravikumar:
Design Issues in Synthesis of Reusable Cores. Great Lakes Symposium on VLSI 1999: 144- - [c36]Nishit Narang, Girish Kumar, C. P. Ravikumar:
Efficient Algorithms for Delay Bounded Multicast Tree Generation for Multimedia Applications. HiPC 1999: 169-173 - [c35]C. P. Ravikumar, Meeta Sharma, Prachi Jain:
Design of WDM Networks for Delay-Bound Multicasting. HiPC 1999: 399-403 - [c34]C. P. Ravikumar, Manish Sharma, R. K. Patney:
Improving the Diagnosability of Digital Circuits. VLSI Design 1999: 629-634 - [c33]C. P. Ravikumar, Ajay Mittal:
Hierarchical Delay Fault Simulation. VLSI Design 1999: 635- - 1998
- [j22]C. P. Ravikumar, Rajneesh Bajpai:
Source-based delay-bounded multicasting in multimedia networks. Comput. Commun. 21(2): 126-132 (1998) - [j21]Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar:
Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems. J. Electron. Test. 12(3): 199-216 (1998) - [j20]Roman Trobec, C. P. Ravikumar:
Parallel Methods for Vlsi Layout Design. IEEE Concurr. 6(1): 87-88 (1998) - [j19]C. P. Ravikumar, Hemant Joshi:
SCOAP-based Testability Analysis from Hierarchical Netlists. VLSI Design 7(2): 131-141 (1998) - [j18]C. P. Ravikumar, Nikhil Sharma:
Testability-Driven Layout of Combinational Circuits. VLSI Design 7(4): 347-352 (1998) - [c32]C. P. Ravikumar, N. Satya Prasad:
Evaluating BIST Architectures for Low Power. Asian Test Symposium 1998: 430-434 - [c31]Nidhi Agrawal, C. P. Ravikumar:
Adaptive Routing Based on Deadlock Recovery. Euro-Par 1998: 981-988 - [c30]Girish Kumar, Nishit Narang, C. P. Ravikumar:
Efficient algorithms for delay-bounded minimum cost path problem in communication networks. HiPC 1998: 141-146 - [c29]C. P. Ravikumar, Dilip R. Pandit, Anubhav Mishra:
Performance-driven design and redesign of high-speed local area networks. HiPC 1998: 416-421 - [c28]Suhrid A. Wadekar, Alice C. Parker, C. P. Ravikumar:
Freedom: Statistical Behavioral Estimation of System Energy and Power. VLSI Design 1998: 30-36 - [c27]C. P. Ravikumar, Sumit Gupta, Akshay Jajoo:
Synthesis of Testable RTL Designs. VLSI Design 1998: 187-192 - [c26]Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar:
Hybrid Testing Schemes Based on Mutual and Signature Testing. VLSI Design 1998: 293- - [c25]Dong-Hyun Heo, Alice C. Parker, C. P. Ravikumar:
An Evolutionary Approach to System Redesign. VLSI Design 1998: 359- - [c24]Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar:
On-Chip Signature Checking for Embedded Memories. VLSI Design 1998: 558-563 - 1997
- [j17]C. P. Ravikumar, Tarun Rai, Varun Verma:
Kautz graphs as attractive logical topologies in multihop lightwave networks. Comput. Commun. 20(14): 1259-1270 (1997) - [j16]C. P. Ravikumar, Nitin Agrawal, Parul Agarwal:
Hierarchical Delay Test Generation. J. Electron. Test. 10(3): 231-244 (1997) - [j15]R. Parthiban, C. P. Ravikumar, R. Kakarala, J. Sivaswamy:
Parallelization of symmetry detection algorithms on a network of workstations. Microprocess. Microsystems 20(6): 341-349 (1997) - [j14]C. P. Ravikumar, C. S. Panda:
Adaptive routing in k-ary n-cubes using incomplete diagnostic information. Microprocess. Microsystems 20(6): 351-360 (1997) - [c23]Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar:
A scheme for multiple on-chip signature checking for embedded SRAMs. ED&TC 1997: 625 - [c22]Ramnik Bajaj, C. P. Ravikumar, Suresh Chandra:
Distributed delay constrained multicast path setup algorithm for high speed networks. HiPC 1997: 438-442 - [c21]Nidhi Agrawal, C. P. Ravikumar:
An Euler Path Based Technique for Deadlock-free Multicasting. ICPP 1997: 378-384 - [c20]Dong-Hyun Heo, Alice C. Parker, C. P. Ravikumar:
Rapid Synthesis of Multi-Chip Systems. VLSI Design 1997: 62-68 - [c19]C. P. Ravikumar, R. Aggarwal, C. Sharma:
A Graph-Theoretic Approach for Register File Based Synthesis. VLSI Design 1997: 118-123 - [c18]Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar:
Efficient Implementation of Multiple On-Chip Signature Checking. VLSI Design 1997: 297-302 - [c17]C. P. Ravikumar, Vikas Jain, Anurag Dod:
Faster Fault Simulation Through Distributed Computing. VLSI Design 1997: 482-487 - 1996
- [j13]Nidhi Agrawal, C. P. Ravikumar:
Fault-tolerant routing in multiply twisted cube topology. J. Syst. Archit. 42(4): 279-288 (1996) - [j12]C. P. Ravikumar, R. Aggarwal:
Parallel search-and-learn techniques and graph coloring. Knowl. Based Syst. 9(1): 3-13 (1996) - [j11]C. P. Ravikumar, Vikram Saxena:
TOGAPS: A Testability Oriented Genetic Algorithm For Pipeline Synthesis. VLSI Design 5(1): 77-87 (1996) - [c16]Nidhi Agrawal, Parul Agarwal, C. P. Ravikumar:
Efficient Delay Test Generation for Modular Circuits. Great Lakes Symposium on VLSI 1996: 220- - [c15]C. P. Ravikumar, Augustine R. Thomas, Abhay Gupta:
A genetic algorithm for assembling optical computers using faulty optical arrays. HiPC 1996: 4-9 - [c14]Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar:
A Novel BIST Architecture With Built-in Self Check. VLSI Design 1996: 57-60 - [c13]C. P. Ravikumar, Rajamani Rajarajan:
Genetic Algorithms for Scan Path Design. VLSI Design 1996: 118-121 - [c12]C. P. Ravikumar, Vikram Saxena:
Synthesis of Testable Pipelined Datapaths Using Genetic Search. VLSI Design 1996: 205-210 - [c11]C. P. Ravikumar, Mukul R. Prasad, Lavmeet S. Hora:
Estimation of Power from Module-level Netlists. VLSI Design 1996: 324-325 - 1995
- [j10]C. P. Ravikumar, Naresh Vedi:
Heuristic and neural algorithms for mapping tasks to a reconfigurable array. Microprocess. Microprogramming 41(2): 137-151 (1995) - [j9]C. P. Ravikumar, Rajender Sethi:
SHARP: A shape recognition system and its parallel implementation. Microprocess. Microsystems 19(3): 131-138 (1995) - [c10]C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal:
A STAFAN-like functional testability measure for register-level circuits. Asian Test Symposium 1995: 192-198 - [c9]C. P. Ravikumar, Hemant Joshi:
HISCOAP: a hierarchical testability analysis tool. VLSI Design 1995: 272-277 - 1994
- [j8]C. P. Ravikumar:
Parallel search-and-learn technique for solving large scale travelling-salesperson problems. Knowl. Based Syst. 7(3): 169-176 (1994) - [j7]C. P. Ravikumar, Haroon Rasheed:
TOPS: A Target-Oriented Partial Scan Design Package Based on Simulated Annealing. VLSI Design 2(3): 233-239 (1994) - [c8]C. P. Ravikumar, G. Manimaran:
Star-Graph based multistage interconnection network for ATM switch fabric. SPDP 1994: 444-451 - [c7]C. P. Ravikumar, Haroon Rasheed:
Simulated Annealing for Target-Oriented Scan. VLSI Design 1994: 107-112 - 1993
- [j6]C. P. Ravikumar:
Solving VLSI physical design problems on a vector machine. Comput. Aided Des. 25(1): 49-57 (1993) - [c6]C. P. Ravikumar, A. Kuchlous, G. Manimaran:
Incomplete Star Graph: An Economical Fault-tolerant Interconnection Network. ICPP (1) 1993: 83-90 - [c5]C. P. Ravikumar:
A Parallel Search-and-Learn Technique for Solving Large Scale TSP. ICTAI 1993: 381-388 - 1992
- [j5]C. P. Ravikumar:
Interval partition with bounded overlap. Comput. Aided Des. 24(8): 405-410 (1992) - [j4]C. P. Ravikumar:
Parallel techniques for solving large scale travelling salesperson problems. Microprocess. Microsystems 16(3): 149-158 (1992) - [c4]C. P. Ravikumar:
Solving Physical Design Problems on a Vector Machine. VLSI Design 1992: 109-116 - 1991
- [j3]C. P. Ravikumar, Sarma Sastry:
VYUHA: A detailed router for multiple routing models. Integr. 11(2): 141-157 (1991) - 1990
- [j2]C. P. Ravikumar, Lalit M. Patnaik:
Performance improvement of simulated annealing algorithms. Comput. Syst. Sci. Eng. 5(2): 111-115 (1990)
1980 – 1989
- 1989
- [j1]C. P. Ravikumar, Sarma Sastry:
A hardware accelerator for hierarchical VLSI routing. Integr. 7(3): 283-302 (1989) - [c3]C. P. Ravikumar, Sarma Sastry:
Parallel Placement on Hypercube Architecture. ICPP (3) 1989: 97-101 - 1988
- [c2]C. P. Ravikumar, Sarma Sastry:
Parallel Placement on Reduced Array Architecture. DAC 1988: 121-127 - 1987
- [c1]C. P. Ravikumar, Lalit M. Patnaik:
An Architecture for CSP and Its Simulation. ICPP 1987: 874-881
Coauthor Index
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