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ORCIDITC 2005: Austin, TX, USA
- Proceedings 2005 IEEE International Test Conference, ITC 2005, Austin, TX, USA, November 8-10, 2005. IEEE Computer Society 2005, ISBN 0-7803-9038-5
- Eric Armengaud
, Florian Rothensteiner, Andreas Steininger, Roman Pallierer, Martin Horauer, Martin Zauner:
A structured approach for the systematic test of embedded automotive communication systems. 8 - Peter Collins, Ilka Reis, Mikko Simonen, Marc van Houcke:
A transparent solution for providing remote wired or wireless communication to board and system level boundary-scan architectures. 8 - Bob Russell:
Verifying flying prober performance - fitness is survival. 8 - Iliya Zamek, Steve Zamek:
Definitions of jitter measurement terms and relationships. 10 - Iliya Zamek, Steve Zamek:
Jitter transformations in measurement instruments and discrepancies between measurement results. 10 - J. Ma, M. Li, M. Marlett:
Third-Order Phase Lock Loop Measurement and Characterization. 56-65 - Kumar L. Parthasarathy, Turker Kuyel, Zhongjun Yu, Degang Chen, Randall L. Geiger:
A 16-bit resistor string DAC with full-calibration at final test. 10 - Amir Zjajo, Henk Jan Bergveld, Rodger Schuttert, José Pineda de Gyvez:
Power-scan chain: design for analog testability. 8 - Adit D. Singh:
A self-timed structural test methodology for timing anomalies due to defects and process variations. 7 - Benjamin N. Lee, Hui Li, Li-C. Wang, Magdy S. Abadir:
Hazard-aware statistical timing simulation and its applications in screening frequency-dependent defects. 10 - Ramyanshu Datta, Sani R. Nassif, Robert K. Montoye, Jacob A. Abraham:
Testing and debugging delay faults in dynamic circuits. 10 - Mack W. Riley, Louis B. Bushard, Nathan Paul Chelstrom, Naoki Kiryu, Steven Ross Ferguson:
Testability features of the first-generation CELL processor. 9 - Nandu Tendolkar, Dawit Belete, Ashutosh Razdan, Hereman Reyes, Bill Schwarz, Marie Sullivan:
Test methodology for Freescale's high performance e600 core based on PowerPC© instruction set architecture. 9 - Mike Tripp, Silvio Picano, Baruch Schnarch:
Drive only at speed functional testing; one of the techniques Intel is using to control test costs. 8 - Chris Schuermyer, Kevin Cota, Robert Madge, Brady Benware:
Identification of systematic yield limiters in complex ASICS through volume structural test fail data visualization and analysis. 9 - Amit Nahar, W. Robert Daasch, Suresh Subramaniam:
Burn-in reduction using principal component analysis. 10 - Andreas Leininger, Peter Muhmenthaler, Wu-Tung Cheng, Nagesh Tamarapalli, Wu Yang, Kun-Han Hans Tsai:
Compression mode diagnosis enables high volume monitoring diagnosis flow. 10 - Chris Jacobsen, Tony Saye, Tom Trader:
Safely backdriving low voltage devices at in-circuit test. 7 - Carlos O'Farrill, Merouane Moakil-Chbany, Bill Eklow:
Optimized reasoning-based diagnosis for non-random, board-level, production defects. 7 - Kenneth P. Parker:
The effects of defects on high-speed boards. 8 - Stephen K. Sunter, Aubin Roy:
Structural tests for jitter tolerance in SerDes receivers. 10 - Sassan Tabatabaei, Freddy Ben-Zeev, Touraj Farahmand:
Jitter spectrum analysis using continuous time interval analyzer (CTIA). 10 - Touraj Farahmand, Sassan Tabatabaei, Freddy Ben-Zeev, André Ivanov:
A DDJ calibration methodology for high-speed test and measurement equipments. 10 - Shalabh Goyal, Abhijit Chatterjee, Mike Atia, Howard Iglehart, Chung Yu Chen, Bassem Shenouda, Nash Khouzam, Hosam Haggag:
Test time reduction of successive approximation register A/D converter by selective code measurement. 8 - Takahiro J. Yamaguchi, Masahiro Ishida, Mani Soma:
A wideband low-noise ATE-based method for measuring jitter in GHz signals. 10 - Soumendu Bhattacharya, Rajarajan Senguttuvan, Abhijit Chatterjee:
Production test enhancement techniques for MB-OFDM ultra-wide band (UWB) devices: EVM and CCDF. 10 - Nisar Ahmed, Mohammad Tehranipoor, C. P. Ravikumar:
Enhanced launch-off-capture transition fault testing. 10 - Narendra Devta-Prasanna, Arun Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz:
Methods for improving transition delay fault coverage using broadside tests. 10 - Jeff Rearick, Richard Rodgers:
Calibrating clock stretch during AC scan testing. 8 - Kees van Kaam, Bart Vermeulen, Henk Jan Bergveld:
Test and debug features of the RTO7 chip. 10 - Olivier Caty, Peter Dahlgren, Ismet Bayraktaroglu:
Microprocessor silicon debug based on failure propagation tracing. 10 - S. Guramurthy, Shobha Vasudevan, Jacob A. Abraham:
Automated mapping of pre-computed module-level test sequences to processor instructions. 10 - W. Robert Daasch, Robert Madge:
Variance reduction and outliers: statistical analysis of semiconductor test data. 9 - W. Robert Daasch, Robert Madge:
Data-driven models for statistical testing: measurements, estimates and residuals. 10 - Robert Madge, Brady Benware, Mark Ward, W. Robert Daasch:
The value of statistical testing for quality, yield and test cost improvement. 10 - Scott Davidson:
Understanding NTF components from the field. 10 - Zoe Conroy, Geoff Richmond, Xinli Gu, Bill Eklow:
A practical perspective on reducing ASIC NTFs. 7 - Anand S. Mudlapur, Vishwani D. Agrawal, Adit D. Singh:
A random access scans architecture to reduce hardware overhead. 9 - Dong Hyun Baik, Kewal K. Saluja:
Progressive random access scan: a simultaneous solution to test power, test data volume and test time. 10 - Arasu T. Senthil, C. P. Ravikumar, Soumitra Kumar Nandy:
A low power and low cost scan test architecture for multi-clock domain SoCs using virtual divide and conquer. 9 - Xinyue Fan, Will R. Moore, Camelia Hora, Guido Gronthoud:
A novel stuck-at based method for transistor stuck-open fault diagnosis. 9 - Ying-Yen Chen, Min-Pin Kuo, Jing-Jia Liou:
Diagnosis framework for locating failed segments of path delay faults. 8 - Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer:
Diagnosis with convolutional compactors in presence of unknown states. 10 - Larry Zhang, Dale Heaton, Hank Largey:
Low cost multisite testing of quadruple band GSM transceivers. 7 - Estella Silva, José Pineda de Gyvez, Guido Gronthoud:
Functional vs. multi-VDD testing of RF circuits. 9 - Erkan Acar, Sule Ozev:
Defect-based RF testing using a new catastrophic fault model. 9 - Chris Schroeder, Jin Pan, Todd Albertson:
A novel process and hardware architecture to reduce burn-in cost. 8 - John Sweeney, Alan Tsefrekas:
Reducing test cost through the use of digital testers for analog tests. 9 - Chris Sellathamby, Md. Mahbub Reja, Lin Fu, Brenda Bai, Edwin Walter Reid, Steven Slupsky, Igor M. Filanovsky, Kris Iniewski:
Noncontact wafer probe using wireless probe cards. 6 - Yu-Ting Lin, David Williams, Tony Ambler:
Cost-effective designs of field service for electronic systems. 8 - Tiziana Margaria, Harald Raffelt, Bernhard Steffen:
Analyzing second-order effects between optimizations for system-level test-based model generation. 7 - Alfredo Benso, Alessandro Cilardo, Nicola Mazzocca, Liviu Miclea, Paolo Prinetto, Szilárd Enyedi:
Reconfigurable systems self-healing using mobile hardware agents. 9 - Zhanglei Wang, Krishnendu Chakrabarty:
Using built-in self-test and adaptive recovery for defect tolerance in molecular electronics-based nanofabrics. 10 - Fei Su, William L. Hwang, Arindam Mukherjee, Krishnendu Chakrabarty:
Defect-oriented testing and diagnosis of digital microfluidics-based biochips. 10 - Woo Cheol Chung, Dong Sam Ha:
A new approach for massive parallel scan design. 10 - Mehrdad Nourani, Arun Radhakrishnan:
Power-supply noise in SoCs: ATPG, estimation and control. 10 - Jing Wang, Ziding Yue, Xiang Lu, Wangqi Qiu, Weiping Shi, D. M. H. Walker:
A vector-based approach for power supply noise analysis in test compaction. 10 - Irith Pomeranz, Sudhakar M. Reddy:
Forming N-detection test sets from one-detection test sets without test generation. 9 - Bill Eklow:
An update on IEEE 1149.6 - successes and issues. 7 - Yervant Zorian, Avetik Yessayan:
IEEE 1500 utilization in SOC design and test. 10 - Gregory A. Maston, Tony Taylor:
Layering of the STIL extensions. 8 - Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki:
Analysis of error-masking and X-masking probabilities for convolutional compactors. 10 - Seongmoon Wang, Kedarnath J. Balakrishnan, Srimat T. Chakradhar:
XWRC: externally-loaded weighted random pattern testing for input test data compression. 10 - Zhanglei Wang, Krishnendu Chakrabarty:
Test data compression for IP embedded cores using selective encoding of scan slices. 10 - Alexandre M. Amory, Eduardo Wenzel Brião, Érika F. Cota, Marcelo Lubaszewski, Fernando Gehm Moraes:
A scalable test strategy for network-on-chip routers. 9 - Qiang Xu, Nicola Nicolici:
On concurrent test of wrapped cores and unwrapped logic blocks in SOCs. 10 - Tom Waayers, Richard Morren, Roberto Grandi:
Definition of a robust modular SOC test architecture; resurrection of the single TAM daisy-chain. 10 - Shu Peng, Sam Wong:
Test implications of lead-free implementation in a high-volume manufacturing environment. 8 - Kenneth P. Parker:
Bead probes in practice. 9 - Rosa D. Reinosa:
Effect of lead free solders on in-circuit test process. 7 - Yi Cai, Amit Bhattacharyya, Joe Martone, Anant Verma, William Burchanowski:
A comprehensive production test solution for 1.5Gb/s and 3Gb/s serial-ATA - based on AWG and undersampling techniques. 8 - Yi Cai, Liming Fang, Robert Ratemo, J. Liu, K. Gross, Michael Kozma:
A test case for 3Gbps serial attached SCSI (SAS). 9 - Mitchell Lin, Kwang-Ting Cheng, Jimmy Hsu, M. C. Sun, Jason Chen, Shelton Lu:
Production-oriented interface testing for PCI-Express by enhanced loop-back technique. 10 - Jody Van Horn:
Towards achieving relentless reliability gains in a server marketplace of teraflops, laptops, kilowatts, and "cost, cost, cost"...: making peace between a black art and the bottom line. 8 - John M. Carulli Jr., Thomas J. Anderson:
Test connections - tying application to process. 8 - Subhasish Mitra, Ming Zhang, T. M. Mak, Norbert Seifert, Victor Zia, Kee Sup Kim:
Logic soft errors: a major barrier to robust platform design. 10 - Grady Giles, Joel Irby, Daniela Toneva, Kun-Han Tsai:
Built-in constraint resolution. 10 - Teresa L. McLaurin, Frank Frederick, Rich Slobodnik:
A methodology for testing one-hot transmission gate multiplexers. 10 - Jeff Remmers, Darin Lee, Richard Fisette:
Hierarchical DFT with enhancements for AC scan, test scheduling and on-chip compression - a case study. 9 - Zoran Stanojevic, Ruifeng Guo, Subhasish Mitra, Srikanth Venkataraman:
Enabling yield analysis with X-compact. 9 - Brion L. Keller, Thomas Bartenstein:
Use of MISRs for compression and diagnostics. 9 - Yu Huang, Wu-Tung Cheng, Janusz Rajski:
Compressed pattern diagnosis for scan chain failures. 8 - Eric N. Tran, Vamsee Krishna, Sujit T. Zachariah, Sreejit Chakravarty:
Logic proximity bridges. 10 - Yuxin Tian, Michael R. Grimaila, Weiping Shi, M. Ray Mercer:
An optimal test pattern selection method to improve the defect coverage. 9 - Kyoung Youn Cho, Subhasish Mitra, Edward J. McCluskey:
Gate exhaustive testing. 7 - Bradford G. Van Treuren, Bryan E. Peterson, José M. Miranda:
JTAG-based vector and chain management for system test. 10 - David Bäckström, Gunnar Carlsson, Erik Larsson:
Remote boundary-scan system test control for the ATCA standard. 10 - Joshua Ferry, Jozef Scesnak, Shoeib Shaikh:
A strategy for board level in-system programmable built-in assisted test and built-in self test. 10 - Jeff Rearick, Bill Eklow, Ken Posse, Al Crouch, Ben Bennetts:
IJTAG (internal JTAG): a step toward a DFT standard. 8 - Andrei Pavlov, Mohamed Azimane, José Pineda de Gyvez, Manoj Sachdev:
Word line pulsing technique for stability fault detection in SRAM cells. 10 - Jin-Fu Li:
Testing priority address encoder faults of content addressable memories. 8 - Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto:
March AB, March AB1: new March tests for unlinked dynamic memory faults. 8 - Theo J. Powell, Amrendra Kumar, Joseph Rayhawk, Nilanjan Mukherjee:
Chasing subtle embedded RAM defects for nanometer technologies. 9 - Koji Asami:
Technique to improve the performance of time-interleaved A-D converters. 7 - Masakatsu Suda, Kazuhiro Yamamoto, Toshiyuki Okayasu, Shusuke Kantake, Satoshi Sudou, Daisuke Watanabe:
CMOS high-speed, high-precision timing generator for 4.266-Gbps memory test system. 9 - Atsushi Oshima, Toshihiro Nomura:
High speed differential pin electronics over 6.4 Gbps. 9 - Brian Arkin:
Lowering the cost of test with a scalable ATE custom processor and timing IC containing 400 high-linearity timing verniers. 6 - Toshiaki Adachi, Ankan K. Pramanick, Mark Elston:
Parallel, multi-DUT testing in an open architecture test system. 9 - Eric Kushnick:
The PXI carrier: a novel approach to ATE instrument development. 7 - William Fritzsche:
Development of a software framework for open architecture ATE. 8 - Eric Liau, Doris Schmitt-Landsiedel:
Computational intelligence based testing for semiconductor measurement systems. 10 - Peter Wohl, John A. Waicukauski, Sanjay Patel, Francisco DaSilva, Thomas W. Williams, Rohit Kapur:
Efficient compression of deterministic patterns into multiple PRPG seeds. 10 - S. Chidambaram, Dimitrios Kagaris, Dhiraj K. Pradhan:
Comparative study of CA with phase shifters and GLFSRs. 10 - Charles H.-P. Wen, Li-C. Wang, Kwang-Ting Cheng, Wei-Ting Liu, Ji-Jan Chen:
Simulation-based target test generation techniques for improving the robustness of a software-based-self-test methodology. 10 - Laung-Terng Wang, Khader S. Abdel-Hafez, Xiaoqing Wen, Boryau Sheu, Shianling Wu, Shyh-Horng Lin, Ming-Tung Chang:
UltraScan: using time-division demultiplexing/multiplexing (TDDM/TDM) with VirtualScan for test cost reduction. 8 - Bin Xue, D. M. H. Walker:
IDDQ test using built-in current sensing of supply line voltage drop. 10 - Balkaran S. Gill, Christos A. Papachristou, Francis G. Wolff, Norbert Seifert:
Node sensitivity analysis for soft errors in CMOS logic. 9 - Kartik Mohanram:
Simulation of transients caused by single-event upsets in combinational logic. 9 - Mesut Meterelliyoz, Hamid Mahmoodi, Kaushik Roy:
A leakage control system for thermal stability during burn-in test. 10 - Iain Robertson, Graham Hetherington, Tom Leslie, Ishwar Parulkar, Ronald Lesnikoski:
Testing high-speed, large scale implementation of SerDes I/Os on chips used in throughput computing systems. 8 - Ishwar Parulkar, Dawei Huang, Leandro Chua Jr., Drew Doblar:
Testing throughput computing interconnect topologies with Tbits/sec bandwidth in manufacturing and in field. 9 - Feng Shi, Yiorgos Makris, Steven M. Nowick, Montek Singh:
Test generation for ultra-high-speed asynchronous pipelines. 10 - Xiaoqing Wen, Yoshiyuki Yamashita, Shohei Morishima, Seiji Kajihara, Laung-Terng Wang, Kewal K. Saluja, Kozo Kinoshita:
Low-capture-power test generation for scan-based at-speed testing. 10 - Nikhil Saluja, Sunil P. Khatri:
Efficient SAT-based combinational ATPG using multi-level don't-cares. 10 - Ilia Polian, John P. Hayes, Sandip Kundu, Bernd Becker:
Transient fault characterization in dynamic noisy environments. 10 - Chong Zhao, Xiaoliang Bai, Sujit Dey:
A static noise impact analysis methodology for evaluating transient error effects in digital VLSI circuits. 10 - Avijit Dutta, Nur A. Touba:
Synthesis of nonintrusive concurrent error detection using an even error detecting function. 8 - Ralf Arnold, Andreas Leininger:
Evaluating ATE-equipment for volume diagnosis. 9 - Greg Maston, Julie Villar:
STIL persistence [data reduction]. 6 - Dan Proskauer:
"Driver on a floppy" delivery of ATE instrumentation software. 8 - Manish Sharma, Wu-Tung Cheng:
X-filter: filtering unknowns from compacted test responses. 9 - Thomas Clouqueur, Kamran Zarrineh, Kewal K. Saluja, Hideo Fujiwara:
Design and analysis of multiple weight linear compactors of responses containing unknown values. 10 - Hung-Mao Lin, James Chien-Mo Li:
Column parity and row selection (CPRS): a BIST diagnosis technique for multiple errors in multiple scan chains. 9 - Ioannis Voyiatzis, Dimitris Gizopoulos, Antonis M. Paschalis, Constantin Halatsis:
A concurrent BIST scheme for on-line/off-line testing based on a pre-computed test set. 8 - Saibal Mukhopadhyay, Kunhyuk Kang, Hamid Mahmoodi, Kaushik Roy:
Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring. 10 - Kuen-Jong Lee, Tong-Yu Hsieh, Melvin A. Breuer:
A novel test methodology based on error-rate to support error-tolerance. 9 - Kaname Yamasaki, Iwao Suzuki, Azumi Kobayashi, Keiichi Horie, Yasuharu Kobayashi, Hideyuki Aoki, Hideki Hayashi, Kenichi Tada, Koki Tsutsumida, Keiichi Higeta:
External memory BIST for system-in-package. 10 - Slimane Boutobza, Michael Nicolaidis, Kheiredine M. Lamara, Andrea Costa:
Programmable memory BIST. 10 - Xiaogang Du, Nilanjan Mukherjee, Wu-Tung Cheng, Sudhakar M. Reddy:
Full-speed field-programmable memory BIST architecture. 9 - Hideo Okawara:
Analysis of pseudo-interleaving AWG. 8 - Le Jin, Kumar L. Parthasarathy, Turker Kuyel, Randall L. Geiger, Degang Chen:
High-performance ADC linearity test using low-precision signals in non-stationary environments. 10 - Chandra Carter, Simon S. Ang:
A test point selection method for data converters using Rademacher functions and wavelet transforms. 10 - Yasuo Sato, Shuji Hamada, Toshiyuki Maeda, Atsuo Takatori, Yasuyuki Nozuyama, Seiji Kajihara:
Invisible delay quality - SDQM model lights up what could not be seen. 9 - Shahdad Irajpour, Sandeep K. Gupta, Melvin A. Breuer:
Multiple tests for each gate delay fault: higher coverage and lower test application cost. 9 - Joel Lurkins, DeAnna Hill, Brady Benware:
Case study: effectiveness of high-speed scan based feed forward voltage testing in reducing DPPM on a high volume ASIC. 7 - Peilin Song, Franco Stellari, Bill Huott, Otto Wagner, Uma Srinivasan, Yuen H. Chan, Rick Rizzolo, H. J. Nam, James P. Eckhardt, Timothy G. McNamara, Ching-Lung Tong, Alan J. Weger, Moyra K. McManus:
An advanced optical diagnostic technique of IBM z990 eServer microprocessor. 9 - Uwe Kerst, Rudolf Schlangen, A. Kabakow, Erwan Le Roy, Ted R. Lundquist, Siegfried Pauthner:
Impact of back side circuit edit on active device performance in bulk silicon ICs. 9 - Ahmed Syed, Richard F. Herlein, Ben Cain, Frank Sauk:
Diagnosis and analysis of an analog circuit failure using time resolved emission microscopy. 7 - Kenneth P. Parker:
A new probing technique for high-speed/high-density printed circuit boards. 10 - Gunnar Carlsson:
How are we going to test SoCs on a board?: the users viewpoint. 1 - Gunnar Carlsson:
How are we going to test socs on a board? the users viewpoint. 1263 - Peter Collins:
How are we going to test SoC's on a PCB? 1 - Gordon D. Robinson:
Board and system test with SoC DFT. 2 - Michael J. Smith:
How are we going to test SOC's on a board? 1 - Rajesh Raina:
Is the concern for soft-error overblown? 1 - Rajesh Galivanche:
Is the concern for soft-error overblown? 1269 - Narayanan Vijaykrishnan:
Soft errors: is the concern for soft-errors overblown? 2 - Rajesh Raina:
Is the concern for soft-error overblown? 2 - Pia N. Sanda:
The concern for soft errors is not overblown. 2 - Fidel Muradali:
Business constraints drive test decisions. 1 - Michael Campbell:
Business constraints drive test decisions planning, partnerships and success. 2 - Paul Domino:
Business constraints drive test decisions. 1 - Jeff Schneider:
Panel: business constraints drive test decisions. 2 - Sanjiv Taneja:
Business constraints drive test decisions - not vice versa. 1 - Scott Davidson:
The ITC test compression shootout. 1 - Shianling Wu, Laung-Terng Wang, Jin Woo Cho, Zhigang Jiang, Boryau Sheu:
Test compression and logic BIST at your fingertips. 2 - Brion L. Keller:
Encounter test OPMISR+ on-chip compression. 2 - Kee Sup Kim:
XMAX: a practical and efficient compression architecture. 2 - Janusz Rajski:
Test compression - real issues and matching solutions. 2 - Nur A. Touba:
Methods for improving test compression. 2 - Rajesh Raina:
Have we overcome the challenges associated with SoC and multi-core testing? 2 - Nathan Chelstrom:
Panel discussion for "have we overcome the challenges associated with SoC and multi-core testing?". 2 - Rajesh Raina:
Have we overcome the challenges associated with SoC and multi-core testing? 2 - Tim Wood:
Position statement: "have we overcome the challenges associated with SoC and multi-core testing?". 1 - Yervant Zorian:
Today's SOC test challenges. 2 - Hosam Haggag, Abhijit Chatterjee:
Panel synopsis: reducing high-speed/RF test cost: guaranteed by design or guaranteed to fail? 1 - Craig Force:
Darwin, thy name is system. 2 - Mustapha Slamani:
Reducing high-speed/RF test cost - guaranteed by design or guaranteed to fail? 1 - Mani Soma:
Guaranteed by design or guaranteed to fail or guaranteed by test? or ... neither? 1 - Stephen K. Sunter:
Correct by construction is guaranteed to fail. 1 - Chris Schuermyer:
Achieving higher yield through diagnosis-the ASIC perspective. 2 - Bruce Cory:
Needs fabless yield ramp foundry partnership to be most successful. 1 - Nagesh Tamarapalli:
Achieving higher yield through diagnosis. 1 - Srikanth Venkataraman:
Achieving higher yield through diagnosis? 2 - James Wang:
Partnering with customer to achieve high yield. 1 - Luis Basto:
The final D-frontier: should DFT be outsourced? 1 - Carl Holzwarth:
Outsourcing DFT: the right mix. 2 - Yu Huang:
Off-shore outsource DFT vs. build off-shore branch offices. 1 - Jeffrey L. Roehr:
The case for outsourcing DFT. 1 - LeRoy Winemberg:
Outsourcing DFT: it can be done but it isn't easy. 2 - Rohit Kapur:
Test the test experts: do we know what we are doing? 1
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