"SystemVerilog-Based Modeling and Verification of 40-Gb/s/Lane PAM-3 ..."

Yong-Gyu Yu et al. (2025)

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DOI: 10.1109/SMACD65553.2025.11092283

access: closed

type: Conference or Workshop Paper

metadata version: 2025-08-20

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Yong-Gyu Yu, Ju-Hyeong Yun, Chae-Hyeon Lim, Joo-Hyung Chae:
SystemVerilog-Based Modeling and Verification of 40-Gb/s/Lane PAM-3 Transmitter for USB4.0 Gen4. SMACD 2025: 1-4

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