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ORCID21st SMACD 2025: Istanbul, Turkiye
- 21st International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design, SMACD 2025, Istanbul, Turkiye, July 7-10, 2025. IEEE 2025, ISBN 979-8-3315-2395-4
- Macit Uluda, Ali Emir Oktem, Günhan Dündar, Arda D. Yalcinkaya:
Integration of CMOS Photodiode and Capacitive Charge Pump Circuits for On Chip Photovoltaic Energy Harvesting. 1-4 - Mohammad Bayazi, Renato Negra:
High-speed, low-power comparators utilizing a self-cascode configuration and a dynamically biased preamplifier technique. 1-4 - Pavlos Stoikos, Olympia Axelou, Pelopidas Tsoumanis, Georgios Ioannis Paliaroutis, George Floros:
Compact SER Models via Model Order Reduction of Diffusion-Based Charge Collection. 1-4 - Yigithan Mehmet Kose
, Utku Guney, Elcin Mert, Dilek Alimli:
Dark Current Analysis in Silicon PIN Photodetectors: TCAD, Lifetime and Statistical Process Control. 1-4 - Sascha Schmalhofer, Yasmine Abu-Haeyeh, Lars Hedrich:
NNHC - a Neural Network to Hardware Compiler. 1-4 - Carlos Almeida, Marco Oliveira, Ricardo Martins:
On the Exploration of Convolutional Variational Autoencoders for Analog Integrated Circuit Post-Placement Performance Regression. 1-4 - Pau Dietz Romero, Caner Toprak, Lammert Duipmans, Stefan van Waasen, Lotte Geck:
Co-Simulation for Automated Optimization of Integrated Cryogenic Qubit Electronics. 1-4 - Enes Saglican, Hakan Taskiran, Kemal Ozanoglu, Engin Afacan:
Design Space Exploration and Topology Assessment of Low-Power Sleep Comparators Using Evolutionary Algorithms. 1-4 - Sevde Vuslat Çikikci, Eren Örek, Ayhan Aysoy, Ali Kagan Özgen, Arda Yavuz, Tuba Ayhan:
A Practical PCB-based Framework for Spiking Neural Networks with a Half-Adder Example. 1-4 - Eda Deniz Demirel, Engin Afacan, Günhan Dündar:
Circuit-Level Modeling and Simulation of Read Disturbance Phenomena: RowHammer and RowPress. 1-4 - Matthias Thiele, Jens Lienig, Menglong He, Kambiz Jamshidi:
Thermal Modeling of Silicon Photonic Waveguides. 1-4 - Hisham M. Elrefai, Wafaa S. Sayed, Ahmed G. Radwan, Lobna A. Said:
Investigation of Reconfigurable CORDIC Modes and Efficiency. 1-4 - Eren Koltuk, Saibe Demir, Eren Yalçin, Kerim Alaz Demir, Ebrar Kahveci, Okan Zafer Batur, Günhan Dündar, Ceyhun Ekrem Kirimli:
A QCM-VNA System for Microfluidic Sensing: Leveraging Higher-Order Harmonics. 1-4 - Milad Bafarassat, Melik Yazici, Korkut Kaan Tokgoz:
FET Modeling with Deep Neural Networks and GAN-Augmented Small Measurement Dataset. 1-4 - Veeti Lahtinen, Altti Heikkinen, Santeri Porrasmaa, Aleksi Tamminen, Marko Kosunen:
An Efficient Framework for Fully Automated Post-layout Simulation-based Optimization. 1-4 - Emirhan Dilekoglu, Mustafa Berke Yelten:
A Large Tuning-Range LC-VCO Design for Mixer-First Type Receivers. 1-4 - Abdulrahman Elsadiq, Hisham M. Elrefai, Lobna A. Said:
FPGA-based Neural Network for Arabic and English Handwritten Digit Recognition. 1-4 - Ceyda Körpe, Kareem Ahmad, Ece Öztürk, Kanishk Tihaiya, Ryanh Tran, Hyunsoo Yang, Junbin Yang, Günhan Dündar, Vincent John Mooney, Kemal Ozanoglu:
A Side-Channel Attack-Resilient Single-Slope ADC for Image Sensor Applications. 1-4 - Simon Wilhelmstätter, Joschua Conrad, Johannes Stark, Devanshi Upadhyaya, Maël Gay, Ilia Polian, Maurits Ortmanns:
1/2CcellV2DD? An Energy Model for Compute-in-Memory SRAM Cells. 1-4 - Lorenz Renner, Ralf Sommer, Yannick Uhlmann:
Application of the Expert Design Plan Methodology on an Ultra-Low-Power Sensor Frontend. 1-4 - Yavuzhan Yavuz, Mustafa Berke Yelten:
A Novel 10-18 GHz Current-Reuse Distributed Cascode Low-Noise Amplifier (LNA) Design. 1-4 - Yong-Gyu Yu, Ju-Hyeong Yun, Chae-Hyeon Lim, Joo-Hyung Chae:
SystemVerilog-Based Modeling and Verification of 40-Gb/s/Lane PAM-3 Transmitter for USB4.0 Gen4. 1-4 - Vassilis Alimisis, Konstantinos Cheliotis, Vasileios Moustakas, Anna Mylona, Zisis Foufas, Paul P. Sotiriadis:
A Power-Efficient Analog Integrated Decision Tree Classifier for Machine Predictive Maintenance Classification. 1-4 - Duarte Marques, Ricardo Martins, Marcelino B. Santos:
Technology-independent Layout Generator of Industry-grade Power Devices Validated Down to 22-nm Nodes. 1-4 - Sandro Junior Della Rovere, Davide Basso, Luca Bortolussi, Mirjana S. Videnovic-Misic, Husni Habal:
Enhancing Reinforcement Learning for the Floorplanning of Analog ICs with Beam Search. 1-4 - Mehmet Selim Mamati, Seref Keser, M. A. Alsunaidi:
A Compact Flexible High-bandwidth Meander Line Patch Antenna for IoT Applications. 1-4 - Andrea Costamagna, Chang Meng, Giovanni De Micheli:
SPFD-Based Delay Resynthesis. 1-4 - Sergio Massaioli, Georges G. E. Gielen:
A Comparative Study of Switch-Mode and Constant-Current Methods for High-Efficiency Neural Stimulation. 1-4 - Taeseung Kang, Taeho Shin, Heejun Kim, Jaeduk Han:
Process-Portable Layout Generation of High-Speed Digital Circuit Using Standard Cells in FinFET. 1-4 - Filipe Azevedo, Markus Leibl, Ricardo Martins, Helmut Graeb:
Inverse Analog IC Sizing and Exploration through Diffusion Models and Structural Knowledge. 1-4 - Lida Kouhalvandi, Sercan Aygun, Serdar Özoguz, Ladislau Matekovits, M. Hassan Najafi, Saeid Karamzadeh:
Power Amplifier Modeling along with Hyperparameter Optimization of LSTM-based DNN through Multi-Verse Optimizer. 1-4 - Mehmet Onur Demirtürk, Berna Ors:
Trust Based Access Control For Dynamically Reconfigurable Sensor Network. 1-4 - Shaheeda F. S. Vajrala, G. S. Javed:
Agile Frequency Synthesis for a sub-100µW Wake-up Receiver. 1-4 - Uxua Esteban-Eraso, Carlos Sánchez-Azqueta, Francisco Aznar, Concepción Aldea, Santiago Celma:
Designing compact phase shifters with a resistorless quadrature signal generator. 1-4 - Afarin Sarrafzadeh, Kuter Erdil, Onur Tavli, Onur Ferhanoglu, Ahmet Can Erten:
Anisotropic and Tunable Vocal Fold Phantom for Biomechanical Modeling. 1-4 - Till Moldenhauer, Yannick Uhlmann, Jürgen Scheible:
An Open-Source Environment for Evaluating Reinforcement Learning Algorithms for Analog IC Floorplanning. 1-4 - Ömer Yusuf Muhikanci, Kemal Ozanoglu, Engin Afacan, Günhan Dündar:
RadiSPICE-L: A Layout-Centric Tool for Radiation-Aware Analog Circuit Design. 1-4 - Mohamed Belguith, Sonia Eloued, Moncef Kadi, Jaleleddine Ben Hadj Slama, Mahmoud Hamouda:
CAD Modeling of a Wafer-Level Packaging GaN Transistors for Electrothermal Simulation Using the Finite Element Method. 1-4 - Konstantinos Cheliotis, Vassilis Alimisis, Vasileios Moustakas, Zisis Foufas, Anna Mylona, Paul P. Sotiriadis:
An Energy-Efficient Analog Integrated Neural Network for Cirrhosis Patient Survival Prediction. 1-4 - Zheng-Hao Wang, Shi-Yu Huang, Chi-Kang Chen:
A Scalable Authentication Scheme for Detecting Unauthorized Dice in A Multi-Die IC. 1-4 - Akif Altintas, Muhammed Yusufoglu, Ugur Cini, Murat Dogruel:
Simulink-Based HDL Design: A Case Study on Harmonic Control Arrays Algorithm Realization. 1-4 - Alexandra Takou, Pelopidas Tsoumanis, Georgios Ioannis Paliaroutis, Nestor E. Evmorfopoulos, George I. Stamoulis:
Fault Injection Attacks Based on Layout-Driven SER Analysis. 1-4 - Shih-Yu Chen, Tzu-Hsiang Wei, Haoju Chang, Hung-Ming Chen, Chien-Nan Jimmy Liu:
Efficient Guard Ring-Aware Placement for FinFET Analog Circuits with Diffusion Sharing. 1-4 - Mert Korkut, Tugba Haykir Ergin, Hüseyin Arda Ülkü:
A Low-Power Charge-Pump PLL for Sub-6 GHz 5G and IoT Wireless Communication Systems. 1-4 - Gustavo Liñán Cembrano, José M. de la Rosa:
Combining Machine Learning and Optimization Techniques for the High-Level Design of Σ∆Ms. 1-4 - Kartikay Mani Tripathi, Madhav Pathak, Sanjeev Manhas, Anand Bulusu:
A Hysteretic-Controlled Digital LDO Regulator for Enhanced Load Transient Response. 1-4 - Adilet Dossanov, Zhaoqun Guo, Uwe Eichler, Benjamin Prautsch, Vadim Issakov:
Low Voltage Bandgap Reference using Intelligent Layout Generators in 22 nm FDSOI CMOS. 1-4 - Fabian Seiler, Peter M. Hinkel, Axel Jantsch, Nima TaheriNejad:
ATOMIC: Automatic Tool for Memristive IMPLY based Circuit-level Simulation and Validation. 1-4 - Sankhya Bhattacharya, Georges G. E. Gielen:
Hybrid AI-Optimization Method for Latent Defect Detection Through Test Transistor Insertion in Analog Circuits. 1-4 - Joseph He Chang, Shekoufeh Neisarian, Nico Mexis, Nikolaos Athanasios Anagnostopoulos, Tolga Arul, Elif Bilge Kavun:
Ternary PUF-based Secure Mutual Authentication Using RNNs for Sequence Learning in Response Classification. 1-4 - Hakan Çetinkaya, Yasin Talay:
Implementation of a Linear LN-TIA with PMOS Resistors in a T-network Configuration. 1-4 - Yijia Hao, Maarten Strackx, Miguel Gandara, Sandy Cochran, Bo Liu:
An AI-driven EDA Algorithm-Empowered VCO and LDO Co-Design Method. 1-4 - Margarida Lourenço, Bingbing Zhao, Junde Li, Marcelino B. Santos, Pui-In Mak, Rui Paulo Martins, Wei-Han Yu, Fábio Passos:
On the Usage of Genetic Algorithms, Reinforcement Learning and Bayesian Optimisation for RF IC Design Automation. 1-4 - Enrique Miranda, E. Piros, Fernando L. Aguirre, X. Pérez, T. Kim, J. P. Schreyer, Jonas Gehrunger, T. Oster, Klaus Hofmann, Jordi Suñé, Christian Hochberger, L. Alff:
Simulation Study of the Maximum Power Dissipation-Energy Consumption Dilemma in Memristors Using the Dynamic Memdiode Model. 1-4 - Ömer Gökalp Akcan, Özlem Koçoglu, Ahmet Can Erten, Onur Ferhanoglu:
A Microfluidic Refreshable Braille Display System. 1-4 - Rashed Al Amin, Roman Obermaisser:
Hardware-Software Co-Design for Resource Efficient Gesture Classification System for FPGAs. 1-4 - Tugce Karpuz, Kemal Ozanoglu, Sumer Can:
A Low-Voltage, Low-Power CMOS Temperature Sensor Utilizing a Single PTAT-CTAT Current Loop. 1-4 - Yasmine Abu-Haeyeh, Sascha Schmalhofer, Lars Hedrich:
Behavioral Modeling of Analog Neural Networks Inference Circuits. 1-4 - F. de Los Santos-Prieto, Deborah Eric, Marc Porti, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández, Montserrat Nafría:
Towards a Reliable PUF Using Organic Thin-Film Transistors. 1-4 - Hakan Taskiran, Enes Saglican, Engin Afacan:
Multi-Objective Optimization of Analog Circuits Using Reinforcement Learning. 1-4 - Hongliang Chen, Weiwei Shi:
A Cost-Efficient Implementation of an SSVEP-Based Brain-Controlled Robotic Arm System. 1-4 - Murad G. K. Alabdullah, N. Seoane, Antonio J. García-Loureiro, K. Kalna:
3D Monte Carlo Simulations of n-type Nanowire-FETs: The Effect of Gate Scaling. 1-4 - Kareem H. Khattab, Muh-Dey Wei, Renato Negra:
Technology-Independent Local Mismatch Estimation Using Precomputed Lookup Tables. 1-4 - Pavlos Stoikos, Olympia Axelou, Pelopidas Tsoumanis, Georgios Ioannis Paliaroutis, George Floros:
Compact SER Models via Model Order Reduction of Diffusion-Based Charge Collection. 1-4 - Veli Nakçi, Mustafa Altun:
Fast and Accurate Multi-Neural Network Ensemble Model. 1-4 - Michele Caselli, Andrea Boni:
Modeling and Analysis of MS Accelerators Embedding SRAM and RRAM Compute Cells. 1-4 - Ahmet Yelboga, Korkut Kaan Tokgoz:
Dynamic Analysis of OOK Modulators Using Eye Diagrams to Assess Data Rate and Output Matching. 1-4 - Mehmet Akif Ozkaya, Kaan Demirel, Tugberk Taha Yolcu, Korkut Kaan Tokgoz:
Response Time Analysis of Thin Film Based Piezoresistive Pressure Sensor. 1-4 - Raúl Aparicio-Téllez, Miguel Garcia-Bosque, Guillermo Díez-Señorans, Santiago Celma:
Temperature Sensors in FPGA Based On Digital Nonlinear Oscillators for Improved Sensitivity. 1-4 - Caglar Ozdag, Engin Afacan, Günhan Dündar:
An Open-Source EM Simulation Flow Based on a High-Level Python API. 1-4 - Anh Nguyen, Chien-Nan Jimmy Liu:
An LLM-assisted Analog IC Design Tool with Automatic Topology Selection and Circuit Sizing. 1-4 - Yoonsoo Park, Songnam Hong, Jaeduk Han:
WDP: A Weighted Delay Prediction Method for Integrated Circuit Interconnects. 1-4 - Fikriye Elif Karakuzu, Eray Kütük, Arda Yildiz, Irem Cömertoglu, Ali Dogus Güngördü, Mustafa Berke Yelten:
A 1 Gb/s PAM-8 Variable-Gain Transimpedance Amplifier (VG-TIA) in 180 nm CMOS Technology. 1-4 - Sennur Güney, Ihsan Çiçek:
Verification of RISC-V R-type Instructions Using A Custom Cocotb Based Approach. 1-4 - Mert Sentürk, Günhan Dündar, Arda Deniz Yalcinkaya:
Optically Powered Sub-1 dB Noise Figure CMOS LNA for Magnetic Resonance Imaging. 1-4 - Roberto Román, Rosario Arjona, Iluminada Baturone:
Multimodal IoT Device Authentication using Behavioral and Physical Unclonable Functions and Kyber Public Key Encryption. 1-5 - Chae-Hyeon Lim, Ju-Hyeong Yun, Yong-Gyu Yu, Joo-Hyung Chae:
SystemVerilog-Based Modeling and Verification of 25.6-GBaud/Lane PAM-3 Receiver. 1-4 - Gabriel López-Pinar, Uxua Esteban-Eraso, Santiago Celma, Carlos Sánchez-Azqueta:
Design of a Low-Noise Amplifier for Qubit Readout. 1-4 - Nilotpal Sarma, Ashutosh Yadav, Sudeb Dasgupta, Anand Bulusu:
Characterization of Inter-Chip Interconnects Using Piecewise Effective Capacitance. 1-4 - Marko S. Andjelkovic, Junchao Chen, Jelisaveta Aleksic, Vishnu Padmakumar, Milos Marjanovic, Nikolaos Zazatis, Trupti Ranjan Lenka, Danijel Dankovic, Christos P. Sotiriou, Fabian Vargas:
Prediction of Single Event Transient Propagation Using Machine Learning Models. 1-4 - Subed Lamichhane, Haotian Lu, Sheldon X.-D. Tan:
EMSpice 2.1: A Coupled EM and IR Drop Analysis Tool with Joule Heating and Thermal Mapb Integration for VLSI Reliability. 1-4 - Jan Rödel, Carna Zivkovic, Neha Chavan, Christoph Grimm:
Efficient Parameter Reduction for Statistical Behavioral Modeling. 1-4 - Engin Çagdas, Hakan Çetinkaya, Oguzhan Kizilbey, Metin Yazgi:
Design of Ultra Wideband Power Divider/Combiner and Comparison on Results of Measurement and Simulation based on EM Solver Methods. 1-4 - Alejandro Casado-Galán, J. Núñez-Martínez, Erica Tena-Sánchez, Francisco Eugenio Potestad-Ordóñez, Antonio J. Acosta:
TERORO - Transient Effect Ring Oscillator and Ring Oscillator Configurable Hybrid PUF. 1-4 - Francesco Gagliardi, Massimo Piotto, Paolo Bruschi, Michele Dei:
Sorting Errors Effects on Optimal Combination Algorithms for Digital-to-Analog Converters. 1-4 - José Costa, Filipe Azevedo, Ricardo Martins:
A Comparative Study on the Incorporation of PVT Corner Conditions within Reinforcement Learning-based Analog IC Sizing Approaches. 1-4 - Muhammed Efdal Elkatmis, Okan Zafer Batur, Burcu Erkmen:
Ultra-Low Power and Low-Leakage Subthreshold CMOS Neural Circuit Design. 1-4
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last updated on 2025-12-09 23:24 CET by the dblp team
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