"A Nonscan Design-for-Testability Method for Register-Transfer-Level ..."

Hideo Fujiwara et al. (2008)

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DOI: 10.1109/TCAD.2008.927757

access: closed

type: Journal Article

metadata version: 2020-09-24

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Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi:
A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9): 1535-1544 (2008)

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