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"Post-processing of clock trees via wiresizing and buffering for robust design."

Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi (1996)

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DOI: 10.1109/43.503938

access: closed

type: Journal Article

metadata version: 2020-09-24

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  - journals/tcad/PullelaMP96
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  - https://dblp.org/rec/journals/tcad/PullelaMP96
Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi:
Post-processing of clock trees via wiresizing and buffering for robust design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(6): 691-701 (1996)

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