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Satyamurthy Pullela
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1990 – 1999
- 1998
- [c6]Satyamurthy Pullela, Rajendran Panda, Abhijit Dharchoudhury, Gopal Vija:
CMOS Combinational Circuit Sizing by Stage-wise Tapering. DATE 1998: 985-986 - 1997
- [j4]Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi:
Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(2): 210-215 (1997) - [j3]Shantanu Ganguly, Daksh Lehther, Satyamurthy Pullela:
Clock Distribution Methodology for PowerPCTM Microprocessors. J. VLSI Signal Process. 16(2-3): 181-189 (1997) - [c5]Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David T. Blaauw:
Library-less synthesis for static CMOS combinational logic circuits. ICCAD 1997: 658-662 - [c4]Abhijit Dharchoudhury, David T. Blaauw, Joe Norton, Satyamurthy Pullela, J. Dunning:
Transistor-level Sizing and Timing Verification of Domino Circuits in the Power PC Microprocessor. ICCD 1997: 143-148 - 1996
- [j2]Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi:
Post-processing of clock trees via wiresizing and buffering for robust design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(6): 691-701 (1996) - 1995
- [c3]Noel Menezes, Satyamurthy Pullela, Lawrence T. Pileggi:
Simultaneous Gate and Interconnect Sizing for Circuit-Level Delay Optimization. DAC 1995: 690-695 - 1994
- [j1]Jessica Qian, Satyamurthy Pullela, Lawrence T. Pillage:
Modeling the "Effective capacitance" for the RC interconnect of CMOS gates. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 13(12): 1526-1535 (1994) - [c2]Noel Menezes, Satyamurthy Pullela, Florentin Dartu, Lawrence T. Pillage:
RC interconnect synthesis-a moment fitting approach. ICCAD 1994: 418-425 - 1993
- [c1]Satyamurthy Pullela, Noel Menezes, Lawrence T. Pillage:
Reliable Non-Zero Skew Clock Trees Using Wire Width Optimization. DAC 1993: 165-170
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