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"A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS."

Jean-Olivier Plouchart et al. (2013)

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DOI: 10.1109/TCSI.2013.2265961

access: closed

type: Journal Article

metadata version: 2020-05-22

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  - journals/tcas/PlouchartFNVSRPBBYPHRTF13
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  persistent URL:
  - https://dblp.org/rec/journals/tcas/PlouchartFNVSRPBBYPHRTF13
Jean-Olivier Plouchart, Mark A. Ferriss, A. S. Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Larry T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman:
A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(8): 2009-2017 (2013)

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